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參數(shù)資料
| 型號(hào)： | μPD45D128164 |
| 廠(chǎng)商： | NEC Corp. |
| 英文描述： | 128 M-bit Synchronous DRAM with Double Data Rate(128 同步動(dòng)態(tài)RAM) |
| 中文描述： | 128 M位同步雙數(shù)據(jù)速率（128同步動(dòng)態(tài)RAM的內(nèi)存） |
| 文件頁(yè)數(shù)： | 11/80頁(yè) |
| 文件大?。?/td> | 637K |
| 代理商： | ΜPD45D128164 |
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11
μ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
2. Commands
Extended mode register set command
(/CS, /RAS, /CAS, /WE Low)
The
μ
PD45D128xxx has an extended mode register that defines enabling or
disabling DLL. In this command, A0 through A11, BA0 and BA1 are the data input
pins.
After power on, the extended mode register set command must be executed to
enabling or disabling DLL.
The extended mode register can be set only when all banks are in idle state.
During 2 CLK (t
RSC
) following this command, the
μ
PD45D128xxx can not accept
any other commands.
Fig.1 Extended mode register set
command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA1
BA0
Mode register set command
(/CS, /RAS, /CAS, /WE Low)
The
μ
PD45D128xxx has a mode register that defines how the device operates. In
this command, A0 through A11, BA0 and BA1 are the data input pins.
After power on, the mode register set command must be executed to initialize the
device.
The mode register can be set only when all banks are in idle state.
During 2 CLK (t
RSC
) following this command, the
μ
PD45D128xxx can not accept
any other commands.
Fig.2 Mode register set command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0,BA1
Bank activate command
(/CS, /RAS = Low, /CAS, /WE = High)
The
μ
PD45D128xxx has four banks, each with 4,096 rows.
This command activates the bank and the row address selected by BA0 and BA1,
and by A0 through A11 respectively.
This command corresponds to a conventional DRAM's /RAS falling.
Fig.3 Bank activate command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0,BA1
Row
Row
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