參數(shù)資料
型號: μPD45D128164
廠商: NEC Corp.
英文描述: 128 M-bit Synchronous DRAM with Double Data Rate(128 同步動態(tài)RAM)
中文描述: 128 M位同步雙數(shù)據(jù)速率(128同步動態(tài)RAM的內存)
文件頁數(shù): 26/80頁
文件大?。?/td> 637K
代理商: ΜPD45D128164
26
μ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
9. Precharge
9.1 Read to Precharge Command Interval
The precharge command can be issued anytime after t
RAS (MIN.)
is satisfied. Soon after the precharge command is
issued, precharge operation performed and the DDR SDRAM enters the idle state after t
RP
is satisfied. The
parameter t
RP
is the time required to perform the precharge.
The earliest timing in a read cycle that a precharge command can be issued without losing any data in the burst is as
follows.
/CAS latency = 2
/CAS latency = 2.5
: (burst length/2) clocks after the read command is issued.
: (burst length/2) clocks after the read command is issued.
CLK
T0
T2
T1
T3
T4
T5
Burst length = 4
Q1
Q2
Q3
READ
DQ
Command
Q4
Q1
Q2
DQ
Command
Q3
Q4
/CAS latency = 2
/CAS latency = 2.5
/CLK
CKE
READ
(Must satisfy t
RAS
)
PRE
PRE
Hi-Z
Hi-Z
DQS
DQS
Hi-Z
Hi-Z
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μPD45D128442 128 M-bit Synchronous DRAM with Double Data Rate(128 同步動態(tài)RAM)
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