參數(shù)資料
型號(hào): μPD45D128164
廠(chǎng)商: NEC Corp.
英文描述: 128 M-bit Synchronous DRAM with Double Data Rate(128 同步動(dòng)態(tài)RAM)
中文描述: 128 M位同步雙數(shù)據(jù)速率(128同步動(dòng)態(tài)RAM的內(nèi)存)
文件頁(yè)數(shù): 31/80頁(yè)
文件大?。?/td> 637K
代理商: ΜPD45D128164
31
μ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
11.2 Write to Write Command Interval
During a write cycle, when new write command is issued, the previous burst will terminate and the new burst will
begin with new write command. WRITE will be interrupted by another WRITE.
The interval between commands is minimum 1 cycle. Each write command can be issued in every clock without any
restriction.
CLK
Burst length = 4
WRITE A
DQS
Command
/CAS latency = 2, 2.5
/CLK
CKE
1 cycle
DA1
DQ
DA2
DB1
DB2
DB3
DB4
WRITE B
T0
T2
T1
T3
T4
T5
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PDF描述
μPD45D128442 128 M-bit Synchronous DRAM with Double Data Rate(128 同步動(dòng)態(tài)RAM)
μPD45D128842 128 M-bit Synchronous DRAM with Double Data Rate(128 同步動(dòng)態(tài)RAM)
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