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參數(shù)資料
| 型號： | μPD45D128164 |
| 廠商： | NEC Corp. |
| 英文描述： | 128 M-bit Synchronous DRAM with Double Data Rate(128 同步動態(tài)RAM) |
| 中文描述： | 128 M位同步雙數(shù)據(jù)速率（128同步動態(tài)RAM的內(nèi)存） |
| 文件頁數(shù)： | 1/80頁 |
| 文件大?。?/td> | 637K |
| 代理商： | ΜPD45D128164 |
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The information in this document is subject to change without notice.
1998
MOS INTEGRATED CIRCUIT
μ
PD45D128442, 45D128842, 45D128164
128 M-bit Synchronous DRAM with Double Data Rate
(4-bank, SSTL_2)
PRELIMINARY DATA SHEET
Document No. M13852EJ1V1DS00 (1st edition)
Date Published December 1998 NS CP(K)
Printed in Japan
The mark
shows major revised points.
Description
The
μ
PD45D128442, 45D128842, 45D128164 are high-speed 134,217,728 bits synchronous dynamic random-
access memories, organized as 8,388,608x4x4, 4194,304x8x4, 2,097,152x16x4 (word x bit x bank), respectively.
The synchronous DRAMs use Double Data Rate (DDR) where data bandwidth is twice of regular synchronous
DRAM.
The synchronous DRAM is compatible with SSTL_2 (Stub Series terminated Logic for 2.5 V).
The synchronous DRAM is packaged in 66-pin Plastic TSOP (II).
Features
Fully Synchronous Dynamic RAM with all input signals except DM, DQS and DQ referenced to a positive clock edge
Double Data Rate interface
Differential CLK (/CLK) input
Data inputs and DM are synchronized with both edges of DQS
Data outputs and DQS are synchronized with a cross point of CLK and /CLK
Quad internal banks operation
Possible to assert random column address in every clock cycle
Programmable Mode register set
/CAS latency (2, 2.5)
Burst length (2, 4, 8)
Wrap sequence (Sequential / Interleave)
Automatic precharge and controlled precharge
Auto refresh (CBR refresh) and self refresh
x4, x8, x16 organization
Byte write control (x4, x8) by DM
Byte write control (x16) by LDM and UDM
2.5 V
±
0.125 V Power supply for Vcc
2.5 V
±
0.125 V Power supply for VccQ
Maximum clock frequency up to 133 MHz
SSTL_2 compatible with all signals
4,096 refresh cycles/64 ms
66-pin Plastic TSOP (II) (400 mil)
Burst termination by Precharge command and Burst stop command
相關(guān)PDF資料 |
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|---|---|
| μPD45D128442 | 128 M-bit Synchronous DRAM with Double Data Rate(128 同步動態(tài)RAM) |
| μPD45D128842 | 128 M-bit Synchronous DRAM with Double Data Rate(128 同步動態(tài)RAM) |
| μPD4811650 | 16M Synchronous Graphics Memory (SGRAM)(16M同步圖形存儲器) |
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