參數(shù)資料
型號: ZPSD612(V)E1
英文描述: Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯,零功耗,4K位SRAM,26個可編程I/O,通用PLD有63個輸入)
中文描述: 現(xiàn)場可編程微控制器外圍設備和嵌入式微-細胞(可編程邏輯,零功耗,4K的位的SRAM,26余個可編程輸入/輸出,通用PLD的有63個輸入)
文件頁數(shù): 67/98頁
文件大小: 484K
代理商: ZPSD612(V)E1
ZPSD6XX(V) Family
12-67
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
CC
V
IH
V
IL
V
IH1
V
IL1
V
HYS
Supply Voltage
All Speeds
4.5
5
5.5
V
High Level Input Voltage
4.5 V < V
CC
< 5.5 V
4.5 V < V
CC
< 5.5 V
(Note 1)
2
V
CC
+.5
0.8
V
Low Level Input Voltage
–0.5
V
Reset High Level Input Voltage
.8 V
CC
–.5
V
CC
+.5
.2 V
CC
–.1
V
Reset Low Level Input Voltage
(Note 1)
V
Reset Pin Hysteresis
0.3
V
V
OL
Output Low Voltage
I
OL
= 20 μA, V
CC
= 4.5 V
0.01
0.1
V
I
OL
= 8 mA, V
CC
= 4.5 V
I
OH
= –20 μA, V
CC
= 4.5 V
0.15
0.45
V
V
OH
Output High Voltage
4.4
4.49
V
I
OH
= –2 mA, V
CC
= 4.5 V
2.4
3.9
V
V
SBY
I
SBY
I
IDLE
V
DF
SRAM Standby Voltage
2.0
V
CC
1
V
SRAM Standby Current
V
CC
= 0 V
V
CC
> V
SBY
Only on V
STBY
0.5
μA
Idle Current (V
STBY
Pin)
SRAM Data Retention Voltage
–0.1
0.1
μA
2
V
I
SB
Standby Supply
Current
Power Down Mode
CSI >V
CC
–.3 V (Note 2)
25
50
μA
Sleep Mode
CSI >V
CC
–.3 V (Note 3)
V
SS
< V
IN
> V
CC
.45 < V
IN
> V
CC
10
20
μA
I
LI
I
LO
Input Leakage Current
–1
±.1
1
μA
Output Leakage Current
–10
±5
10
μA
ZPLD_TURBO = OFF,
f = 0 MHz (Note 4)
Figure 31
I
CC
(DC)
(Note 4a)
Operating
Supply Current
ZPLD Only
ZPLD_TURBO = ON,
f = 0 MHz
400
700
μA/PT
ZPLD AC Base
Figure 31
CMiser = ON,
8-Bit Bus Mode
EPROM AC Adder
0.8
2
mA/MHz
All Other Cases
1.8
4
mA/MHz
I
CC
(AC)
(Note 4a)
CMiser = ON,
8-Bit Bus Mode
1.4
2.7
mA/MHz
SRAM AC Adder
CMiser = ON,
16-Bit Bus Mode
2
4
mA/MHz
CMiser = OFF
3.8
7.5
mA/MHz
DC Characteristics
(5 V ± 10% Versions)
NOTES:
1.
Reset input has hysteresis. V
IL1
is valid at or below .2V
CC
–.1. V
IH1
is valid at or above .8V
CC
.
CSI deselected or internal PD is active.
Sleep mode bit is set and internal PD is active.
See ZPLD ICC/Frequency Power Consumption graph for details.
4a. I
OUT
= 0 mA
2.
3.
4.
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