參數(shù)資料
型號(hào)： ZPSD612(V)E1
英文描述： Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，零功耗，4K位SRAM,26個(gè)可編程I/O,通用PLD有63個(gè)輸入)
中文描述： 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備和嵌入式微-細(xì)胞（可編程邏輯，零功耗，4K的位的SRAM，26余個(gè)可編程輸入/輸出，通用PLD的有63個(gè)輸入）
文件頁(yè)數(shù)： 61/98頁(yè)
文件大?。?/td> 484K
代理商： ZPSD612(V)E1
ZPSD6XX(V) Family
12-61
Power
Management
Unit
(cont.)
Other Power Saving Options
The ZPSD6XX(V) offers other reduced power saving options that are independent of the
Power Down or Sleep Mode. Except for the SRAM Standby and CSI input features, they are
enabled by setting bits in the PMMR 0 register.
J
CMiser Bit
The CMiser bit resides in PMMR0. This bit controls the AC power consumption and
access time of the EPROM and SRAM. When in 8-bit data bus mode and CMiser is set,
the ZPSD6XX(V) will consume the lowest level of AC power. However, the access time
will be slower (see CMiser adder in timing parameters). When CMiser bit is off, the AC
power is higher and the ZPSD6XX(V) will return to standard access time.
J
SRAM Standby Mode
The SRAM has a dedicated Vstby pin (PC2) that can be connected to a battery.
When V
CC
becomes lower than Vstby then the ZPSD6XX(V) will automatically connect
the Vstby as a power source to the SRAM. The SRAM Standby Current (Istby) is
typically 0.5μA. SRAM data retention voltage is 2V minimum.
J
The CSI Input
Pin PD2 of Port D can be configured in PSDsoft as the CSI input . When low, the signal
selects and enables the internal EPROM and SRAM for read or write operations.
A high on the CSI pin will disable the EPROM and SRAM and reduce the PSD power
consumption. However, the ZPLD remains operational when CSI is high.
J
Zero Power ZPLD
The power and speed of the ZPLD is controlled by the Turbo bit (bit 3) in the PMMR0.
After reset the ZPLD is in Turbo mode and runs at full power and speed. By setting the
bit to one, the Turbo mode is disabled and the ZPLD is consuming Zero Power current
if the inputs are not switching for an extended time of 70ns. The propagation delay time
will be increased by 10ns after the Turbo bit is set to one (turned off) if the inputs
change at a frequency of less than 15MHz.
The Turbo bit and CMiser are independent of each other. The Turbo bit controls only
the ZPLD DC power and propagation delay. The CMiser bit affects the EPROM and
SRAM AC power and access time only.
J
Input Clock
The ZPSD6XX(V) provides the option to turn off the CLKIN input to the ZPLD to save
AC power consumption. The CLKIN is an input to the ZPLD AND array and the Output
Micro
Cells. During power down or if any of the CLKIN input is not being used as part
of the ZPLD logic equation, the clock should be disabled to save AC power.
The CLKIN will be disconnected from the ZPLD AND array or the Micro
Cells by
setting bit 4 or 5 to “1” in the PMMR0.
相關(guān)PDF資料
PDF描述
ZPSD613(V)E1 Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，零功耗，4K位SRAM,26個(gè)可編程I/O,通用PLD有63個(gè)輸入)
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