參數(shù)資料
型號： ZPSD612(V)E1
英文描述： Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，零功耗，4K位SRAM,26個可編程I/O,通用PLD有63個輸入)
中文描述： 現(xiàn)場可編程微控制器外圍設備和嵌入式微-細胞（可編程邏輯，零功耗，4K的位的SRAM，26余個可編程輸入/輸出，通用PLD的有63個輸入）
文件頁數(shù)： 51/98頁
文件大?。?/td> 484K
代理商： ZPSD612(V)E1
ZPSD6XX(V) Family
12-51
I/O Ports
(cont.)
Port C – Functionality and Structure
Port C does not support Address Out mode and the Control Register is not required.
Port C can be configured to perform one or more of the following functions:
J
MCU I/O Mode
J
GPLD Output – McellC outputs can be connected to Port C pins
J
GPLD Input – Via the eight Input Micro
Cells
J
Address In – Additional high address inputs using the Input Micro
Cells.
J
Open Drain – Port C pins can be configured in Open Drain Mode
Port C pin PC2 is dedicated as the Vstby pin for SRAM battery backup and can not be used
for other functions. Pin PC7 may be configured as the WRH input in certain microcontroller
interface designs.
Port D – Functionality and Structure
Port D has only three I/O pins, does not support Address Out mode, and no Control
Register is required. Port D can be configured to perform one or more of the following
functions:
J
MCU I/O Mode
J
ECSPLD Output – External chip select output
J
ZPLD Input – direct input to ZPLD, no Input Micro
Cells
J
Slew rate – pins can be set up for fast slew rate
Port D pins can be configured in PSDsoft as input pins for other dedicated functions:
J
PD0 – ALE, as address strobe input
J
PD1 – CLKIN, as clock input to the Micro
Cells Flip-Flops and APD counter
J
PD2 – CSI, as active low chip select input. A high input will disable
the PSD EPROM/SRAM.
相關PDF資料
PDF描述
ZPSD613(V)E1 Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，零功耗，4K位SRAM,26個可編程I/O,通用PLD有63個輸入)
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