參數(shù)資料
型號： ZPSD612(V)E1
英文描述： Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，零功耗，4K位SRAM,26個(gè)可編程I/O,通用PLD有63個(gè)輸入)
中文描述： 現(xiàn)場可編程微控制器外圍設(shè)備和嵌入式微-細(xì)胞（可編程邏輯，零功耗，4K的位的SRAM，26余個(gè)可編程輸入/輸出，通用PLD的有63個(gè)輸入）
文件頁數(shù)： 55/98頁
文件大小： 484K
代理商： ZPSD612(V)E1
ZPSD6XX(V) Family
12-55
Bit 7
PIO_EN
Bit 6* Bit 5* Bit 4* Bit 3* Bit 2*
Bit 1
RD_EN
Bit 0
PSEN_EN
0 = disable
PIO mode
0 = RD access
SRAM, I/O
0 = PSEN access
EPROM only
1 = enable
PIO mode
1 = RD access
EPROM,
SRAM, I/O
1 = PSEN access
EPROM,
SRAM, I/O
Table 29. VM Register
*
Bit 6-2 are not used, set to “0”.
Memory Select for 8031 Microcontrollers
The 8031 family of microcontrollers, including 80C251 and 80C51XA, has a separate
address space for code memory (enabled by PSEN) and data memory (enabled by RD).
The ZPSD6XX(V) allows the EPROM and SRAM to reside in the program space, data
space or both. Three different configurations are possible:
J
Separate Space Mode
Code memory space is separated from data memory space. The PSEN signal is used
to access the program code from the EPROM, and the RD signal is used to access
data from the SRAM and I/O Ports. This is the default configuration.
J
Combined Space Mode
The program and data memory spaces are combined into one 64KB block space that
allows the EPROM or SRAM to be accessed by either PSEN or RD. The EPROM and
SRAM blocks address space must not overlap. This mode is enabled by the
microcontroller by setting the bits in the VM Register as shown in Table 29. If Bit 0
is “1”, either PSEN or RD can access the SRAM. If Bit 1 is a “1”, either RD or PSEN
can access the EPROM. Figure 27 shows the memory select logic for Combined
Space Mode.
J
Mixed Mode
Allows individual EPROM blocks to be configured in either Data Space or Program
Space. EPROM block chip selects must be qualified with the 8031 RD input in the
ES0–ES7 equations. An active low RD will select EPROM blocks in data space and
disable the blocks that are in program space. For EPROM blocks that reside in data
space, the access time is calculated from RD valid to data valid. This mode is set
automatically by PSDsoft whenever the RD signal is included in the EPROM chip
select equations.
Memory Blocks
(cont.)
相關(guān)PDF資料
PDF描述
ZPSD613(V)E1 Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，零功耗，4K位SRAM,26個(gè)可編程I/O,通用PLD有63個(gè)輸入)
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