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| 型號： | ZPSD612(V)E1 |
| 英文描述： | Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，零功耗，4K位SRAM,26個可編程I/O,通用PLD有63個輸入) |
| 中文描述： | 現(xiàn)場可編程微控制器外圍設(shè)備和嵌入式微-細(xì)胞（可編程邏輯，零功耗，4K的位的SRAM，26余個可編程輸入/輸出，通用PLD的有63個輸入） |
| 文件頁數(shù)： | 16/98頁 |
| 文件大?。?/td> | 484K |
| 代理商： | ZPSD612(V)E1 |
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ZPSD6XX(V) Family
12-16
The ZPLDs can minimize power consumption by switching off when inputs remain
unchanged for an extended time of about 70ns. Setting the Turbo mode bit to off (Bit 3 of
the PMMR0 register) automatically places the ZPLDs into standby if no inputs are changing.
Turbo off mode increases propagation delays while reducing power consumption. Refer to
the Power Management Unit on how to set up the Turbo Bit. Power is further reduced by the
PSDsoft development tools which disables unused product terms.
Each of the three ZPLDs has unique characteristics suited for its applications. They are
described in the following sections.
Decode PLD
The Decode PLD (DPLD), shown in Figure 5, is used to select the internal ZPSD6XX(V)
functions: EPROM blocks, SRAM, Registers (CSIOP) and the Port A Peripheral Mode.
All the select signals are active high and have one product term, except ES7 which has two.
The CSIOP is the select line for the ZPSD6XX(V) internal registers that occupies 256 bytes
of memory space. A second level decoder selects a register based on the address
inputs A[7-0].
Each EPROM block has its own chip select. The chip select of the eighth EPROM
block has two product terms, ES7A and ES7B. This allows the eighth block to reside
in two memory spaces, where ES7B can typically select reset vectors or configuration
bytes that are stored in the MCU address space.
PSEL 0 & 1 are used as inputs to Port A to control the port’s Peripheral I/O mode
operation. Usually PSEL 0&1 are defined in term of the MCU address inputs. This mode is
explained in the I/O Port section.
ZPLDs
(cont.)
Input Source
Input Name
Number of Bits
MCU Address Bus
A[15:0]
*
16
I/O Ports A, B, and C
PA[7:0], PB[7:0]
PC[7:3], PC[1:0]
23
Page Register
PGR[3:0]
4
Control Signal
CNTL1 (Read)
1
Reset Pin
RESET
1
Table 7. DPLD Inputs
*
NOTE:
The address inputs are A[19:4] in 80C51XA mode, A[3:0] are assigned to Port A.
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