參數(shù)資料
型號： XRT83VSH38
廠商： Exar Corporation
英文描述： 8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
中文描述： 8通道的T1/E1/J1短途線路接口單元
文件頁數(shù)： 5/76頁
文件大?。?/td> 722K
代理商： XRT83VSH38
XRT83VSH38
I
REV. 1.0.7
8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
TABLE OF CONTENTS
GENERAL DESCRIPTION.............................................................................................................. 1
A
PPLICATIONS
............................................................................................................................................................... 1
F
IGURE
1. B
LOCK
D
IAGRAM
OF
THE
XRT83VSH38 T1/E1/J1 LIU (H
OST
M
ODE
) .................................................................................... 1
F
IGURE
2. B
LOCK
D
IAGRAM
OF
THE
XRT83VSH38 T1/E1/J1 LIU (H
ARDWARE
M
ODE
) ........................................................................... 2
F
EATURES
..................................................................................................................................................................... 3
ORDERING INFORMATION ....................................................................................................................3
T
ABLE
OF
C
ONTENTS
............................................................................................................
I
PIN DESCRIPTION BY FUNCTION................................................................................................ 5
R
ECEIVE
S
ECTION
......................................................................................................................................................... 5
T
RANSMIT
S
ECTION
....................................................................................................................................................... 7
P
ARALLEL
M
ICROPROCESSOR
I
NTERFACE
...................................................................................................................... 9
JITTER
A
TTENUATOR
.................................................................................................................................................... 11
C
LOCK
S
YNTHESIZER
.................................................................................................................................................. 11
A
LARM
F
UNCTIONS
/R
EDUNDANCY
S
UPPORT
................................................................................................................. 13
S
ERIAL
M
ICROPROCESSOR
I
NTERFACE
......................................................................................................................... 15
P
OWER
AND
G
ROUND
.................................................................................................................................................. 15
FUNCTIONAL DESCRIPTION...................................................................................................... 18
1.0 HARDWARE MODE VS HOST MODE ................................................................................................18
1.1 FEATURE DIFFERENCES IN HARDWARE MODE ...................................................................................... 18
T
ABLE
1: D
IFFERENCES
B
ETWEEN
H
ARDWARE
M
ODE
AND
H
OST
M
ODE
................................................................................................. 18
2.0 MASTER CLOCK GENERATOR .........................................................................................................19
F
IGURE
3. T
WO
I
NPUT
C
LOCK
S
OURCE
................................................................................................................................................. 19
F
IGURE
4. O
NE
I
NPUT
C
LOCK
S
OURCE
................................................................................................................................................. 19
T
ABLE
2: M
ASTER
C
LOCK
G
ENERATOR
................................................................................................................................................. 19
3.0 RECEIVE PATH LINE INTERFACE ....................................................................................................20
F
IGURE
5. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
R
ECEIVE
P
ATH
............................................................................................................ 20
3.1 LINE TERMINATION (RTIP/RRING) .............................................................................................................. 20
3.1.1 CASE 1: INTERNAL TERMINATION.......................................................................................................................... 20
T
ABLE
3: S
ELECTING
THE
I
NTERNAL
I
MPEDANCE
................................................................................................................................... 20
F
IGURE
6. T
YPICAL
C
ONNECTION
D
IAGRAM
U
SING
I
NTERNAL
T
ERMINATION
.......................................................................................... 20
3.1.2 CASE 2: INTERNAL TERMINATION WITH ONE EXTERNAL FIXED RESISTOR FOR ALL MODES .................... 21
T
ABLE
4: S
ELECTING
THE
V
ALUE
OF
THE
E
XTERNAL
F
IXED
R
ESISTOR
.................................................................................................... 21
F
IGURE
7. T
YPICAL
C
ONNECTION
D
IAGRAM
U
SING
O
NE
E
XTERNAL
F
IXED
R
ESISTOR
............................................................................. 21
3.2 CLOCK AND DATA RECOVERY ................................................................................................................... 22
F
IGURE
8. R
ECEIVE
D
ATA
U
PDATED
ON
THE
R
ISING
E
DGE
OF
RCLK..................................................................................................... 22
F
IGURE
9. R
ECEIVE
D
ATA
U
PDATED
ON
THE
F
ALLING
E
DGE
OF
RCLK................................................................................................... 22
T
ABLE
5: T
IMING
S
PECIFICATIONS
FOR
RCLK/RPOS/RNEG ................................................................................................................ 22
3.2.1 RECEIVE SENSITIVITY.............................................................................................................................................. 22
F
IGURE
10. T
EST
C
ONFIGURATION
FOR
M
EASURING
R
ECEIVE
S
ENSITIVITY
............................................................................................ 23
3.2.2 INTERFERENCE MARGIN ......................................................................................................................................... 23
F
IGURE
11. T
EST
C
ONFIGURATION
FOR
M
EASURING
I
NTERFERENCE
M
ARGIN
......................................................................................... 23
3.2.3 GENERAL ALARM DETECTION AND INTERRUPT GENERATION........................................................................ 23
3.3 RECEIVE JITTER ATTENUATOR .................................................................................................................. 24
3.4 HDB3/B8ZS DECODER .................................................................................................................................. 25
3.5 RPOS/RNEG/RCLK ........................................................................................................................................ 25
F
IGURE
12. S
INGLE
R
AIL
M
ODE
W
ITH
A
F
IXED
R
EPEATING
"0011" P
ATTERN
......................................................................................... 25
F
IGURE
13. D
UAL
R
AIL
M
ODE
W
ITH
A
F
IXED
R
EPEATING
"0011" P
ATTERN
............................................................................................ 25
3.6 RXMUTE (RECEIVER LOS WITH DATA MUTING) ....................................................................................... 26
F
IGURE
14. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
R
X
MUTE F
UNCTION
................................................................................................... 26
4.0 TRANSMIT PATH LINE INTERFACE .................................................................................................27
F
IGURE
15. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
T
RANSMIT
P
ATH
......................................................................................................... 27
4.1 TCLK/TPOS/TNEG DIGITAL INPUTS ............................................................................................................ 27
F
IGURE
16. T
RANSMIT
D
ATA
S
AMPLED
ON
F
ALLING
E
DGE
OF
TCLK...................................................................................................... 27
F
IGURE
17. T
RANSMIT
D
ATA
S
AMPLED
ON
R
ISING
E
DGE
OF
TCLK........................................................................................................ 27
T
ABLE
6: T
IMING
S
PECIFICATIONS
FOR
TCLK/TPOS/TNEG.................................................................................................................. 28
4.2 HDB3/B8ZS ENCODER .................................................................................................................................. 28
T
ABLE
7: E
XAMPLES
OF
HDB3 E
NCODING
............................................................................................................................................ 28
T
ABLE
8: E
XAMPLES
OF
B8ZS E
NCODING
............................................................................................................................................. 28
4.3 TRANSMIT JITTER ATTENUATOR ............................................................................................................... 29
相關(guān)PDF資料
PDF描述
XRT83VSH38IB 8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
XRT84L14 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT84L18 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT84L38 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT84L38_06 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT83VSH38ES 功能描述:外圍驅(qū)動器與原件 - PCI 8CH T1/E1LIUSH (low cost version) RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT83VSH38IB 功能描述:接口 - 專用 8CH SH T1/E1 Line RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59
XRT83VSH38IB-F 功能描述:外圍驅(qū)動器與原件 - PCI 8 Channel Short-Haul RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT83VSH38IB-F 制造商:Exar Corporation 功能描述:T1/E1 LIU IC
XRT84L38 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*