參數(shù)資料
型號(hào)： XRT83VSH38
廠商： Exar Corporation
英文描述： 8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
中文描述： 8通道的T1/E1/J1短途線路接口單元
文件頁(yè)數(shù)： 46/76頁(yè)
文件大?。?/td> 722K
代理商： XRT83VSH38
XRT83VSH38
43
8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.7
6.3
The Microprocessor Interface Block Signals
The LIU may be configured into different operating modes and have its performance monitored by software
through a standard microprocessor using data, address and control signals. These interface signals are
described below in
Table 14
,
Table 15
, and
Table 16
. The microprocessor interface can be configured to
operate in Intel mode or Motorola mode. When the microprocessor interface is operating in Intel mode, some
of the control signals function in a manner required by the Intel 80xx family of microprocessors. Likewise, when
the microprocessor interface is operating in Motorola mode, then these control signals function in a manner as
required by the Motorola microprocessors. (For using a Motorola 68K asynchronous processor, see
Figure 36
and
Table 18
)
Table 14
lists and describes those microprocessor interface signals whose role is
constant across the two modes.
Table 15
describes the role of some of these signals when the microprocessor
interface is operating in the Intel mode. Likewise,
Table 16
describes the role of these signals when the
microprocessor interface is operating in the Motorola Power PC mode.
T
ABLE
14: XRT83VSH38 M
ICROPROCESSOR
I
NTERFACE
S
IGNALS
THAT
EXHIBIT
CONSTANT
ROLES
IN
BOTH
I
NTEL
AND
M
OTOROLA
M
ODES
P
IN
N
AME
T
YPE
D
ESCRIPTION
μ
PTS[2:1]
I
Microprocessor Interface Mode Select Input pins
These two pins are used to specify the microprocessor interface mode. The relationship
between the state of these two input pins, and the corresponding microprocessor mode is pre-
sented in
Table 13
.
DATA[7:0]
I/O
Bi-Directional Data Bus for register "Read" or "Write" Operations.
ADDR[7:0]
I
Eight-Bit Address Bus Inputs
The XRT83VSH38 LIU microprocessor interface uses a direct address bus. This address bus
is provided to permit the user to select an on-chip register for Read/Write access.
CS
I
Chip Select Input
This active low signal selects the microprocessor interface of the XRT83VSH38 LIU and
enables Read/Write operations with the on-chip register locations.
T
ABLE
15: I
NTEL
MODE
: M
ICROPROCESSOR
I
NTERFACE
S
IGNALS
XRT83VSH38
P
IN
N
AME
I
NTEL
E
QUIVALENT
P
IN
T
YPE
D
ESCRIPTION
ALE
ALE
I
Address-Latch Enable:
This active high signal is used to latch the contents on
the address bus ADDR[7:0]. The contents of the address bus are latched into the
ADDR[7:0] inputs on the falling edge of ALE.
RD_DS
RD
I
Read Signal:
This active low input functions as the read signal from the local
μ
P.
When this pin is pulled “Low” (if CS is “Low”) the LIU is informed that a read oper-
ation has been requested and begins the process of the read cycle.
WR_R/W
WR
I
Write Signal:
This active low input functions as the write signal from the local
μ
P.
When this pin is pulled “Low” (if CS is “Low”) the LIU is informed that a write
operation has been requested and begins the process of the write cycle.
RDY
RDY
O
Ready Output:
This active low signal is provided by the LIU device. It indicates
that the current read or write cycle is complete, and the LIU is waiting for the next
command.
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