參數(shù)資料
型號(hào)： XRT83VSH316IB
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： 16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
中文描述： DATACOM, PCM TRANSCEIVER, PBGA316
封裝： 21 X 21 MM, STBGA-316
文件頁(yè)數(shù)： 57/96頁(yè)
文件大小： 600K
代理商： XRT83VSH316IB
PRELIMINARY
16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
XRT83VSH316
55
REV. P1.0.3
6.4
If the LIU is interfaced to an Intel type μP, then it should be configured to operate in the Intel mode. Intel type
Read and Write operations are described below.
Intel Mode Read Cycle
Whenever an Intel-type μP wishes to read the contents of a register, it should do the following.
1.
Place the address of the target register on the address bus input pins ADDR[9:0].
2.
While the μP is placing this address value on the address bus, the address decoding circuitry should
assert the CS pin of the LIU, by toggling it "Low". This action enables further communication between the
μP and the LIU microprocessor interface block.
3.
Toggle the ALE input pin "High". This step enables the address bus input drivers, within the microproces-
sor interface block of the LIU.
4.
The μP should then toggle the ALE pin "Low". This step causes the LIU to latch the contents of the address
bus into its internal circuitry. At this point, the address of the register has now been selected.
5.
Next, the μP should indicate that this current bus cycle is a Read operation by toggling the RD input pin
"Low". This action also enables the bi-directional data bus output drivers of the LIU.
6.
After the μP toggles the Read signal "Low", the LIU will toggle the RDY output pin "Low". The LIU does this
in order to inform the μP that the data is available to be read by the μP, and that it is ready for the next com-
mand.
7.
After the μP detects the RDY signal and has read the data, it can terminate the Read Cycle by toggling the
RD input pin "High".
N
OTE
:
ALE can be tied “High” if this signal is not available.
The Intel Mode Write Cycle
Whenever an Intel type μP wishes to write a byte or word of data into a register within the LIU, it should do the
following.
1.
Place the address of the target register on the address bus input pins ADDR[9:0].
2.
While the μP is placing this address value on the address bus, the address decoding circuitry should
assert the CS pin of the LIU, by toggling it "Low". This action enables further communication between the
μP and the LIU microprocessor interface block.
3.
Toggle the ALE input pin "High". This step enables the address bus input drivers, within the microproces-
sor interface block of the LIU.
4.
The μP should then toggle the ALE pin "Low". This step causes the LIU to latch the contents of the address
bus into its internal circuitry. At this point, the address of the register has now been selected.
5.
The μP should then place the byte or word that it intends to write into the target register, on the bi-direc-
tional data bus DATA[7:0].
6.
Next, the μP should indicate that this current bus cycle is a Write operation by toggling the
WR
input pin
"Low". This action also enables the bi-directional data bus input drivers of the LIU.
7.
After the μP toggles the Write signal "Low", the LIU will toggle the RDY output pin "Low". The LIU does this
in order to inform the μP that the data has been written into the internal register location, and that it is ready
for the next command.
N
OTE
:
ALE can be tied “High” if this signal is not available.
The Intel Read and Write timing diagram is shown in
Figure 40
. The timing specifications are shown in
Table 20
.
Intel Mode Programmed I/O Access (Asynchronous)
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