參數(shù)資料
型號(hào): XRT83VSH316IB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: 16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
中文描述: DATACOM, PCM TRANSCEIVER, PBGA316
封裝: 21 X 21 MM, STBGA-316
文件頁(yè)數(shù): 34/96頁(yè)
文件大?。?/td> 600K
代理商: XRT83VSH316IB
XRT83VSH316
PRELIMINARY
32
16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. P1.0.3
4.2
In single rail mode, the LIU can encode the TPOS input signal to AMI or HDB3/B8ZS data. In E1 mode and
HDB3 encoding selected, any sequence with four or more consecutive zeros in the input will be replaced with
000V or B00V, where "B" indicates a pulse conforming to the bipolar rule and "V" representing a pulse violating
the rule. An example of HDB3 encoding is shown in
Table 7
. In T1 mode and B8ZS encoding selected, an
input data sequence with eight or more consecutive zeros will be replaced using the B8ZS encoding rule. An
example with Bipolar with 8 Zero Substitution is shown in
Table 8
.
HDB3/B8ZS Encoder
4.3
The XRT83VSH316 LIU is ideal for multiplexer or mapper applications where the network data crosses
multiple timing domains. As the higher data rates are de-multiplexed down into T1 or E1 data, stuffing bits are
typically removed which can leave gaps in the incoming data stream. The transmit jitter attenuator can be
enabled with a 32-Bit or 64-Bit FIFO that is used to smooth the gapped clock into a steady T1 or E1 output.
The maximum gap width of the 16-Channel LIU is shown in
Table 9
.
Jitter Attenuator (If enabled in the Transmit Path)
N
OTE
:
If the LIU is used in a loop timing system, the jitter attenuator can be placed in the receive path. See the Receive
Section of this datasheet.
T
ABLE
7: E
XAMPLES
OF
HDB3 E
NCODING
N
UMBER
OF
P
ULSES
B
EFORE
N
EXT
4 Z
EROS
Input
0000
HDB3 (Case 1)
Odd
000V
HDB3 (Case 2)
Even
B00V
T
ABLE
8: E
XAMPLES
OF
B8ZS E
NCODING
C
ASE
P
RECEDING
P
ULSE
N
EXT
8 B
ITS
Case 1
Input
+
00000000
B8ZS
000VB0VB
AMI Output
+
000+-0-+
Case 2
Input
-
00000000
B8ZS
000VB0VB
AMI Output
-
000-+0+-
T
ABLE
9: M
AXIMUM
G
AP
W
IDTH
FOR
M
ULTIPLEXER
/M
APPER
A
PPLICATIONS
FIFO D
EPTH
M
AXIMUM
G
AP
W
IDTH
32-Bit
20 UI
64-Bit
50 UI
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