參數(shù)資料
型號: XRT83VSH316IB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: 16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
中文描述: DATACOM, PCM TRANSCEIVER, PBGA316
封裝: 21 X 21 MM, STBGA-316
文件頁數(shù): 30/96頁
文件大?。?/td> 600K
代理商: XRT83VSH316IB
XRT83VSH316
PRELIMINARY
28
16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. P1.0.3
3.9
The receive jitter attenuator reduces phase and frequency jitter in the recovered clock if it is enabled. The jitter
attenuator uses a data FIFO (First In First Out) with a programmable depth of 32-bit or 64-bit. If the LIU is used
for line synchronization (loop timing systems), the JA should be enabled in the receive path. When the Read
and Write pointers of the FIFO are within 2-Bits of over-flowing or under-flowing, the bandwidth of the jitter
attenuator is widened to track the short term input jitter, thereby avoiding data corruption. When this condition
occurs, the jitter attenuator will not attenuate input jitter until the Read/Write pointer’s position is outside the 2-
Bit window. In T1 mode, the bandwidth of the JA is always set to 3Hz. In E1 mode, the bandwidth is
programmable to either 10Hz or 1.5Hz (1.5Hz automatically selects the 64-Bit FIFO depth). The JA has a
clock delay equal to of the FIFO bit depth.
Jitter Attenuator (If enabled in the Receive Path)
N
OTE
:
If the LIU is used in a multiplexer/mapper application where stuffing bits are typically removed, the jitter attenuator
can be placed in the transmit path to smooth out the gapped clock. See the Transmit Section of this datasheet.
3.10
HDB3/B8ZS Decoder
In single rail mode, RPOS can decode AMI or HDB3/B8ZS signals. For E1 mode, HDB3 is defined as any
block of 4 successive zeros replaced with 000V or B00V, so that two successive V pulses are of opposite
polarity to prevent a DC component. In T1 mode, 8 successive zeros are replaced with 000VB0VB. If the
HDB3/B8ZS decoder is selected, the receive path removes the V and B pulses so that the original data is
output to RPOS.
3.10.0.1
RPOS/RNEG/RCLK
The digital output data can be programmed to either single rail or dual rail formats.
Figure 13
is a timing
diagram of a repeating "0011" pattern in single-rail mode.
Figure 14
is a timing diagram of the same fixed
pattern in dual rail mode.
F
IGURE
13. S
INGLE
R
AIL
M
ODE
W
ITH
A
F
IXED
R
EPEATING
"0011" P
ATTERN
F
IGURE
14. D
UAL
R
AIL
M
ODE
W
ITH
A
F
IXED
R
EPEATING
"0011" P
ATTERN
RCLK
RPOS
0
0
0
1
1
RCLK
RPOS
0
0
0
1
1
RNEG
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