參數(shù)資料
型號(hào): XRT83VSH28IB
廠商: EXAR CORP
元件分類(lèi): 數(shù)字傳輸電路
英文描述: 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
中文描述: DATACOM, PCM TRANSCEIVER, PBGA225
封裝: 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-225
文件頁(yè)數(shù): 63/74頁(yè)
文件大?。?/td> 574K
代理商: XRT83VSH28IB
PRELIMINARY
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
XRT83VSH28
60
REV. P1.0.0
T
ABLE
32: M
ICROPROCESSOR
R
EGISTER
0
X
0E
H
B
IT
D
ESCRIPTION
C
HANNEL
0-7 (0
X
0E
H
-0
X
7E
H
)
B
IT
N
AME
F
UNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved
This Register Bit is Not Used
X
0
D[6:0]
7SEG[6:0]
Segment Number Seven, Same Description as Register 0x08h
R/W
T
ABLE
33: M
ICROPROCESSOR
R
EGISTER
0
X
0F
H
B
IT
D
ESCRIPTION
C
HANNEL
0-7 (0
X
0F
H
-0
X
7F
H
)
B
IT
N
AME
F
UNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved
This Register Bit is Not Used
X
0
D[6:0]
8SEG[6:0]
Segment Number Eight, Same Description as Register 0x08h
R/W
T
ABLE
34: M
ICROPROCESSOR
R
EGISTER
0
X
80
H
, B
IT
D
ESCRIPTION
R
EGISTER
A
DDRESS
0
X
80
H
N
AME
F
UNCTION
R
EGISTER
T
YPE
R
ESET
V
ALUE
B
IT
#
D7
SR/DR
Single-rail/Dual-rail Select:
Writing a “1” to this bit configures
all 4channels in the XRT83VSH28 to operate in the Single-rail
mode.
Writing a “0” configures the XRT83VSH28 to operate in Dual-
rail mode.
R/W
0
D6
ATAOS
Automatic Transmit All Ones Upon RLOS:
Writing a “1” to
this bit enables the automatic transmission of All "Ones" data
to the line for the channel that detects an RLOS condition.
Writing a “0” disables this feature.
R/W
0
D5
RCLKE
Receive Clock Edge:
Writing a “1” to this bit selects receive
output data of all channels to be updated on the negative edge
of RCLK.
Wring a “0” selects data to be updated on the positive edge of
RCLK.
R/W
0
D4
TCLKE
Transmit Clock Edge:
Writing a “0” to this bit selects transmit
data at TPOS_n/TDATA_n and TNEG_n/CODES_n of all
channels to be sampled on the falling edge of TCLK_n.
Writing a “1” selects the rising edge of the TCLK_n for sam-
pling.
R/W
0
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