參數(shù)資料
型號: XRT83VSH28IB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
中文描述: DATACOM, PCM TRANSCEIVER, PBGA225
封裝: 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-225
文件頁數(shù): 58/74頁
文件大?。?/td> 574K
代理商: XRT83VSH28IB
XRT83VSH28
PRELIMINARY
55
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
REV. P1.0.0
D1
INSBER
Insert Bit Error
When this bit transitions from a "0" to a "1", a bit error will be
inserted in the transmitted QRSS/PRBS pattern. The state of this
bit will be sampled on the rising edge of TCLK. To ensure proper
operation, it is recommended to write a "0" to this bit before writing
a "1".
R/W
0
D0
Reserved
T
ABLE
23: M
ICROPROCESSOR
R
EGISTER
0
X
04
H
B
IT
D
ESCRIPTION
C
HANNEL
0-7(0
X
04
H
-0
X
74
H
)
B
IT
N
AME
F
UNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved
This Register Bit is Not Used.
D6
DMOIE
Digital Monitor Output Interrupt Enable
0 = Masks the DMO function
1 = Enables Interrupt Generation
R/W
0
D5
FLSIE
FIFO Limit Status Interrupt Enable
0 = Masks the FLS function
1 = Enables Interrupt Generation
R/W
0
D4
LCV/OFIE
Line Code Violation / Counter Overflow Interrupt Enable
0 = Masks the LCV/OF function
1 = Enables Interrupt Generation
R/W
0
D3
Reserved
This Register Bit is Not Used.
D2
AISIE
Alarm Indication Signal Interrupt Enable
0 = Masks the AIS function
1 = Enables Interrupt Generation
R/W
0
D1
RLOSIE
Receiver Loss of Signal Interrupt Enable
0 = Masks the RLOS function
1 = Enables Interrupt Generation
R/W
0
D0
QRPDIE
Quasi Random Signal Source Interrupt Enable
0 = Masks the QRPD function
1 = Enables Interrupt Generation
R/W
0
T
ABLE
22: M
ICROPROCESSOR
R
EGISTER
0
X
03
H
B
IT
D
ESCRIPTION
C
HANNEL
0-7 (0
X
03
H
-0
X
73
H
)
B
IT
N
AME
F
UNCTION
Register
Type
Default
Value
(HW reset)
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