參數(shù)資料
型號: XRT83VSH28IB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
中文描述: DATACOM, PCM TRANSCEIVER, PBGA225
封裝: 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-225
文件頁數(shù): 23/74頁
文件大小: 574K
代理商: XRT83VSH28IB
PRELIMINARY
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
XRT83VSH28
20
REV. P1.0.0
2.0
RECEIVE PATH LINE INTERFACE
The receive path of the XRT83VSH28 LIU consists of 8 independent E1 receivers. The following section
describes the complete receive path from RTIP/RRING inputs to RCLK/RPOS/RNEG outputs. A simplified
block diagram of the receive path is shown in
Figure 3
.
F
IGURE
3. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
R
ECEIVE
P
ATH
2.1
Line Termination (RTIP/RRING)
2.1.1
CASE 1: Internal Termination
The input stage of the receive path accepts standard E1 twisted pair or E1 coaxial cable inputs through RTIP
and RRING. The physical interface is optimized by placing the terminating impedance inside the LIU. This
allows one bill of materials for all modes of operation reducing the number of external components necessary
in system design. The receive termination impedance is selected by programming TERSEL[1:0] to match the
line impedance. Selecting the internal impedance is shown in
Table 2
.
The XRT83VSH28 has the ability to switch the internal termination to "High" impedance by programming
RxTSEL in the appropriate channel register. For internal termination, set RxTSEL to "1". By default, RxTSEL
is set to "0" ("High" impedance). For redundancy applications, a dedicated hardware pin (RxTSEL) is also
available to control the receive termination for all channels simultaneously. This hardware pin takes priority
over the register setting if RxTCNTL is set to "1" in the appropriate global register. If RxTCNTL is set to "0", the
state of this pin is ignored. See
Figure 4
for a typical connection diagram using the internal termination.
F
IGURE
4. T
YPICAL
C
ONNECTION
D
IAGRAM
U
SING
I
NTERNAL
T
ERMINATION
T
ABLE
2: S
ELECTING
THE
I
NTERNAL
I
MPEDANCE
TERSEL[1:0]
R
ECEIVE
T
ERMINATION
0h (00)
Reserved
1h (01)
Reserved
2h (10)
75
3h (11)
120
HDB3 Decoder
Rx Jitter
Attenuator
Clock & Data
Recovery
Peak Detector
& Slicer
RTIP
RRING
RCLK
R
TIP
R
RING
XRT83VSH28 LIU
1:1
Internal Impedance
Line Interface E1
One Bill of Materials
Receiver
Input
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