參數(shù)資料
型號(hào)： XRT81L27
廠商： Exar Corporation
英文描述： Seven Channel E1 Line Interface Unit with Clock Recovery(7通道 E1線接口單元（帶時(shí)鐘恢復(fù)）)
中文描述： 七通道E1線路接口單元的時(shí)鐘恢復(fù)（7通道素E1線接口單元（帶時(shí)鐘恢復(fù)））
文件頁(yè)數(shù)： 8/28頁(yè)
文件大小： 140K
代理商： XRT81L27
XRT81L27
SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY
REV. P1.0.1
PRELIMINARY
8
58
RPOS6/RDATA6
O
Receiver 6 Positive Data Output:
In dual-rail mode, this signal is the receive p-rail output data.
Receiver 6 NRZ Data Output:
In single-rail mode, this signal is the receive output data.
59
RNEG6/LCV6
O
Receiver 6 Negative Data Output:
In dual-rail mode, this signal is the receive n-rail output data.
Line Code Violation Output:
In single-rail mode, this signal output High for one clock cycle to indicate a
code violation is detected in the received data. If AMI coding is selected,
every bipolar violation received will cause this pin to go High.
60
RClk6
O
Receiver 6 Clock Output.
61
LOS7
O
Receiver 7 Loss of Signal:
This signal is asserted High to indicate loss of signal at the receive input.
62
RPOS7/RDATA7
O
Receiver 7 Positive Data Output:
In dual-rail mode, this signal is the receive p-rail output data.
Receiver 7 NRZ Data Output:
In single-rail mode, this signal is the receive output data.
63
RNEG7/LCV7
O
Receiver 6 Negative Data Output:
In dual-rail mode, this signal is the receive n-rail output data.
Line Code Violation Output:
In single-rail mode, this signal output High for one clock cycle to indicate a
code violation is detected in the received data. If AMI coding is selected,
every bipolar violation received will cause this pin to go High.
64
RClk76
O
Receiver 7 Clock Output.
65
RClkP
I
Receiver Clock Output Polarity:
In Hardware Mode and with this pin tied to Low, All channel RPOS /RDATA
and RNEG/LCV output data are updated on the falling edge of RClk. Tie this
pin High to select data update on rising edge of RClk. Internally pulled-down
with 50KW.
66
TClkP
I
Transmit Clock Polarity:
In Hardware Mode and with this pin tied to Low, transmit input data is sam-
pled using the falling edge of TClk. Tie this pin High to select rising edge of
TClk for data sampling. Internally pulled-down with 50KW.
67
RRING7
I
Receiver 7 Bipolar Negative Input:
68
RTIP7
I
Receiver 7 Bipolar Positive Input:
69
SR/DR
I
Single-rail/Dual-rail Select:
In Hardware Mode and with this pin tied to High, input transmit data and
receive output data is selected for single-rail mode operation.
Tie this pin Low to select dual-rail mode. Internally pulled-down with 50K
.
70
MClk
I
Master Clock Input:
This signal is an independent 2.048MHz clock with accuracy better than
±50ppm and duty cycle within 40% to 60%. The function of MCLK is to pro-
vide timing source for the PLL clock recovery circuit, reference clock to insert
All Ones data in the transmit as well as the receive paths.
71
TGND6
****
Transmitter 6 Supply Ground
72
TRing6
O
Transmitter 6 Ring Output:
Negative bipolar data output to the line
P
IN
#
N
AME
T
YPE
D
ESCRIPTION
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