參數(shù)資料
型號(hào)： XRT81L27
廠商： Exar Corporation
英文描述： Seven Channel E1 Line Interface Unit with Clock Recovery(7通道 E1線接口單元（帶時(shí)鐘恢復(fù)）)
中文描述： 七通道E1線路接口單元的時(shí)鐘恢復(fù)（7通道素E1線接口單元（帶時(shí)鐘恢復(fù)））
文件頁數(shù)： 3/28頁
文件大?。?/td> 140K
代理商： XRT81L27
XRT81L27
PRELIMINARY
SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY
REV. P1.0.1
III
TABLE OF CONTENTS
GENERAL DESCRIPTION .................................................................................................. 1
F
EATURES
................................................................................................................................................... 1
A
PPLICATIONS
.............................................................................................................................................. 1
Figure 1. Block Diagram ................................................................................................................................... 1
O
RDERING
I
NFORMATION
....................................................................................................................... 2
Figure 2. Pin Out of the XRT81L27 .................................................................................................................. 2
TABLE OF CONTENTS .................................................................................................................................... I
PIN DESCRIPTIONS ........................................................................................................... 3
T
ABLE
1: R
ECEIVER
E
LECTRICAL
C
HARACTERISTICS
.......................................................................................... 12
T
ABLE
2: T
RANSMITTER
E
LECTRICAL
C
HARACTERISTICS
.................................................................................... 13
Figure 3. Transmit Input Timing ...................................................................................................................... 13
Figure 4. Receive Output Timing .................................................................................................................... 14
T
ABLE
3: DC E
LECTRICAL
C
HARACTERISTICS
.................................................................................................... 14
T
ABLE
4: M
ICROPROCESSOR
R
EGISTER
A
DDRESS
AND
C
ONTROL
...................................................................... 15
T
ABLE
5: R
EGISTER
C
ONTROL
B
IT
D
ESCRIPTION
............................................................................................... 16
Figure 5. Timing Diagram for the Microprocessor Serial Interface ................................................................. 18
Figure 6. XRT81L27 Microprocessor serial Interface Timing ......................................................................... 19
T
ABLE
6: AC E
LECTRICAL
C
HARACTERISTICS
.................................................................................................... 20
T
ABLE
7: P
ER
C
HANNEL
P
OWER
C
ONSUMPTION
INCLUDING
LINE
POWER
DISSIPATION
,
TRANSMISSION
AND
RECEIVE
PATHS
ALL
ACTIVE
.............................................................................................................................. 20
Figure 7. Illustration of the ITU-T G.703 Pulse Template for E1 Applications ................................................ 21
1.0 The Pulse Shaping Circuit ............................................................................................................... 21
1.1 I
NTERFACING
THE
T
RANSMIT
S
ECTIONS
OF
THE
XRT81L27
TO
THE
L
INE
.......................................................... 21
Figure 8. Illustration of how to interface the Transmit Sections of the XRT81L27 to the Line (for 75W Applications)
22
Figure 9. Illustration of how to interface the Transmit Sections the XRT81L27 to the Line (for 120W Applications)
23
2.0 The Receive Section ........................................................................................................................ 23
2.1 I
NTERFACING
THE
R
ECEIVE
S
ECTIONS
TO
THE
L
INE
........................................................................................... 23
Figure 10. Recommended Schematic for Interfacing the Receive Sections of the XRT81L27 to the Line for 75W
Applications (Transformer-Coupling) ............................................................................................ 24
Figure 11. Recommended Schematic for Interfacing the Receive Sections of the XRT81L27 to the Line for 120W
Applications (Transformer-Coupling) ............................................................................................ 24
Figure 12. Recommended Schematic for Interfacing the Receive Sections of the XRT81L27 to the Line for 120W
Applications (Capacitive-Coupling) .............................................................................................. 25
2.2 T
HE
R
ECEIVE
E
QUALIZER
B
OCK
....................................................................................................................... 25
2.3 T
HE
P
EAK
D
ETECTOR
AND
S
LICER
B
LOCK
....................................................................................................... 25
2.4 T
HE
LOS D
ETECTOR
BLOCK
............................................................................................................................ 25
Figure 13. Package Outline Drawing .............................................................................................................. 26
R
EVISIONS
................................................................................................................................................. 27
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