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參數(shù)資料
| 型號： | XRT81L27 |
| 廠商： | Exar Corporation |
| 英文描述： | Seven Channel E1 Line Interface Unit with Clock Recovery(7通道 E1線接口單元（帶時鐘恢復(fù)）) |
| 中文描述： | 七通道E1線路接口單元的時鐘恢復(fù)（7通道素E1線接口單元（帶時鐘恢復(fù)）） |
| 文件頁數(shù)： | 26/28頁 |
| 文件大?。?/td> | 140K |
| 代理商： | XRT81L27 |
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XRT81L27
SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY
REV. P1.0.1
PRELIMINARY
26
Figure 12, presents a recommended method to use
when capacitive-coupling the Receive Section to the
line.
2.2
After a given Channel (within the XRT81L27 device)
has received the incoming line signal, via the RTIP_x
and RRing_x input pins, the first block that this signal
will pass through is the Receive Equalizer block.
As the line signal is transmitted from a given Trans-
mitting terminal, the pulse shapes (at that location)
are basically square. Hence, these pulses consist of
a combination of low and high frequency Fourier com-
ponents. As this line signal travels from the transmit-
ting terminal (via the coaxial cable or twisted pair) to
the receiving terminal, it will be subjected to frequen-
cy-dependent loss. The higher frequency compo-
nents of the signal will be subjected to a greater
amount of attenuation than the lower
frequency components. If this line signal travels over
reasonably long cable lengths, then the shape of the
pulses (which were originally square) will be distorted
and with inter-symbol interference increases.
The purpose of this block is to equalize the incoming
distorted signal, due to cable loss. In essence, the
Receive Equalizer block accomplishes this by sub-
jecting the received line signal to frequency-depen-
dent amplification (which attempts to counter the fre-
quency-dependent loss that the line signal has expe-
rienced). By doing this, the Receive Equalizer is at-
T
HE
R
ECEIVE
E
QUALIZER
B
OCK
tempting to restore the shape of the line signal so that
the received data can be recovered reliably.
2.3
T
HE
P
EAK
D
ETECTOR
AND
S
LICER
B
LOCK
After the incoming line signal has passed through the
Receive Equalizer block, it will next be routed to the
Slicer block. The purpose of the Slicer block is to
quantify a given bit-period (or symbol) within the in-
coming line signal as either a “1” or a “0”.
2.4
T
HE
LOS D
ETECTOR
BLOCK
The LOS Detector block, within each channel (of the
XRT81L27 device) was specifically designed to com-
ply
with the LOS Declaration/Clearance requirements per
ITU-T G.775. As a consequence, the channel will de-
clare an LOS Condition, (by driving the LOS output
pin “High”) if the received line signal amplitude drops
to –20dB or below. Further, the channel will clear the
LOS Condition if the signal amplitude rises back up to
–15dB typically, or above. The XRT81L27 was de-
signed to meet the ITU-T G.775 specification timing
requirements for declaring and clearing the LOS indi-
cator. In particular, the XRT81L27 will declare an LOS
between 10 and 255 UI ( or E1 bit periods) after the
actual time the LOS condition occurred. Further, the
XRT81L27 will clear the LOS indicator within 10 to
255 UI after restoration of the incoming line signal.
F
IGURE
12. R
ECOMMENDED
S
CHEMATIC
FOR
I
NTERFACING
THE
R
ECEIVE
S
ECTIONS
OF
THE
XRT81L27
TO
THE
L
INE
FOR
120W A
PPLICATIONS
(C
APACITIVE
-C
OUPLING
)
30.1
30.1
1
I
6
C1
C2
0.1uF
0.1uF
RTIP1
RRing1
RPOS1
RNEG1
RLOS1
RClk1
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