
XRT79L71
REV. P1.0.3
PRELIMINARY
1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
á
84
CHANNEL INTERRUPT INDICATION REGISTERS
3
Transmit
UTOPIA/POS-PHY
Interface Block Interrupt
Enable
R/W
Transmit UTOPIA/POS-PHY Interface Block Interrupt
Enable:
This READ/WRITE bit permit the user to either enable or disable
the Transmit UTOPIA/POS-PHY Interface Block for interrupt
generation. If the user writes a "0" to this register bit and dis-
ables the "Transmit UTOPIA/POS-PHY Interface Block" (for
interrupt generation), then all "Transmit UTOPIA/POS-PHY Inter-
face Block" interrupts will be disabled for interrupt generation. If
the user writes a "1" to this register bit, he/she will still need to
enable the individual "Transmit UTOPIA/POS-PHY Interface
Block" interrupt(s) at the "Source Level" in order to enable that
particular interrupt.
0 - Disable all "Transmit UTOPIA/POS-PHY Interface Block"
interrupts within the device.
1 - Enables the "Transmit UTOPIA/POS-PHY Interface Block" at
the "Block-Level".
2 - 1
Unused
R/O
0
Transmit ATM Cell/PPP
Processor Block
Interrupt Enable
R/W
Transmit ATM Cell/PPP Processor Block Interrupt Enable:
This READ/WRITE bit permit the user to either enable or disable
the Transmit ATM Cell/PPP Processor Block for interrupt genera-
tion. If the user writes a "0" to this register bit and disables the
"Transmit ATM Cell/PPP Processor Block" (for interrupt genera-
tion), then all "Transmit ATM Cell/PPP Processor Block" inter-
rupts will be disabled for interrupt generation. If the user writes a
"1" to this register bit, he/she will still need to enable the individ-
ual "Transmit ATM Cell/PPP Processor Block" interrupt(s) at the
"Source Level" in order to enable that particular interrupt.
0 - Disable all "Transmit ATM Cell/PPP Processor Block" inter-
rupts within the device.
1 - Enables the "Transmit ATM Cell/PPP Processor Block" at the
"Block-Level".
CHANNEL INTERRUPT INDICATOR - RECEIVE CELL PROCESSOR/PPP PROCESSOR BLOCK
(ADDRESS = 0X0119)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Unused
Receive Cell
Processor
Block
Interrupt
R/O
R/O
0
0
B
IT
N
UMBER
N
AME
T
YPE
D
ESCRIPTION
7 - 1
Unused
R/O
B
IT
N
UMBER
N
AME
T
YPE
D
ESCRIPTION