Rev.1.01 XRD98L63 Figure 29. Application Schematic Vdd 12 ASIC/DSP Timing Generator Serial Interface Controls (These controls can be accesse" />
參數(shù)資料
型號(hào): XRD98L63ZEVAL
廠商: Exar Corporation
文件頁(yè)數(shù): 29/41頁(yè)
文件大?。?/td> 0K
描述: EVAL BOARD FOR XRD98L63
標(biāo)準(zhǔn)包裝: 1
系列: *
35
Rev.1.01
XRD98L63
Figure 29. Application Schematic
Vdd
12
ASIC/DSP
Timing Generator
Serial Interface
Controls
(These controls can be
accessed via the serial
interface as well)
CCD
Digital Video Input
0.01
F
0.01
F
0.1
F
18.2K
C1=0.1
F decoupling capacitors at each supply pin
C1
15V
37
48
1
12
24
13
36
25
XRD98L63
AVDD
n/c
CCDIN
REFIN
VCM
AVDD
n/c
AGND
n/c
Fsync
DVDD
PBLK
EOS
CLAMP
SPIX
SBLK
CAL
ADCLK
OGND
OVDD
DGND
BiasRes
AVDD
TestOut
CapN
CapP
RESET
PD
SCLK
LOAD
SDI
AGND
OE
DB7
DB6
DB5
DB4
DB3
DB1
DB2
DB0
DB8
DB10
DB9
DB11
3
C1
3
Vdd
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