Rev.1.01 LINE RATE CLOCKS CLAMP, CAL & PBLK are the three line rate clock signals. There are two modes of operation for these c" />
參數(shù)資料
型號(hào)： XRD98L63ZEVAL
廠商： Exar Corporation
文件頁(yè)數(shù)： 21/41頁(yè)
文件大小： 0K
描述： EVAL BOARD FOR XRD98L63
標(biāo)準(zhǔn)包裝： 1
系列： *
XRD98L63
28
Rev.1.01
LINE RATE CLOCKS
CLAMP, CAL & PBLK are the three line rate clock
signals. There are two modes of operation for these
clocks, the CAL & CLAMP mode, and the CALonly
mode.
EOS can be a line rate clock as well, but it is only used
in the Multiple Gain mode. Please refer to the Multiple
Gain mode section for information about EOS.
CAL & CLAMP Mode
CAL & CLAMP is the default line timing mode
(CALonly=0). In this mode, the CLAMP signal is used
to activate the DC restore Clamp at the CDS input, and
the CAL signal is used to define the Optical Black
pixels to be used for the Black Level calibration
function. Typically the CLAMP pulse comes during the
dummy or optical black pixels at the beginning of each
scan line, and the CAL pulse comes during the longer
string of optical black pixels at the end of each scan
line. CLAMP & CAL must not be active at the same
time.
CAL-Only (OneShot) Mode
In this mode, the CAL signal is used to activate the DC
restore clamp and to define the optical black pixels for
calibration. The CAL pulse should frame the longest
group of OB pixels at either the end or beginning of
each line. The DC restore Clamp switch is turned ON
during the first four pixels of each CAL pulse. The
remaining pixels under the CAL pulse are used for
black level calibration.
Enable the CAL-Only mode by writing a "1" to the
"CALonly" bit in the Clock register.
PBLK (Pre-Blanking Clock)
The function of PBLK is the same in both CAL and
CLAMP mode and CAL-Only (One Shot) mode. It is
used to disconnect the CDS from the CCD input signal
during the vertical shift time between CCD lines. If
PBLK and CAL overlap, the CAL signal will overide so
that black level calibration can take place.
If the DOclamp (digital output clamp) option is enabled,
PBLK will also force the digital output bus, DB[11:0], to
the value in the Serial Interface Offset register,
OB[7:0].
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