Rev.1.01 PIN CONFIGURATION Figure 2. XRD98L63 Pinout Figure 1. XRD98L63 Block Diagram CDS 12-bit ADC Digital Noise Suppression CDAC " />
參數(shù)資料
型號(hào): XRD98L63ZEVAL
廠商: Exar Corporation
文件頁數(shù): 12/41頁
文件大小: 0K
描述: EVAL BOARD FOR XRD98L63
標(biāo)準(zhǔn)包裝: 1
系列: *
XRD98L63
2
Rev.1.01
PIN CONFIGURATION
Figure 2. XRD98L63 Pinout
Figure 1. XRD98L63 Block Diagram
CDS
12-bit ADC
Digital Noise
Suppression
CDAC
FDAC
Offset Calibration
Logic
DB[11:0]
REFIN
Gain[9:0]
AVDD
AGND
OVDD
OGND
DVDD
DGND
Serial
Interface
Timing
Logic
SDI
SCLK
LOAD
FSYNC
CLAMP
CAL
SPIX
SBLK
ADCLK
Bias
BIASRES
CAPN
PD
RESET
OE
Readback data
to output mux
Readback
data from
Serial Interface
RBenable
CCDIN
+
PGA
CAPP
Black Level
Offset Calibration
Loop
Gain[9:0]
Averager
Hot
Pixel
Clipper
18.2 K
NoCDS
ADCin
PBLK
EOS
VCM
Gain
Logic
Reg
37
DB7
DB6
DB5
DB4
DB3
DB1
FSYNC
AVDD
N/C
CCDIN
REFIN
BIASRES
38
39
40
41
42
43
44
45
46
47
48
1 2
3
4 5 6
7 8
9 10 11 12
24
23
22
21
20
19
18
17
16
15
14
13
36 35 34 33 32 31 30 29 28 27 26 25
XRD98L63
(top view)
DB2
DB0
AVDD
DVDD
DB8
DB10
DB9
DB11
PBLK
VCM
AVDD
N/C
TESTOUT
CAPN
CAPP
EOS
RESET
PD
SCLK
LOAD
SDI
AGND
OE
AGND
CLAMP
SPIX
SBLK
CAL
ADCLK
OGND
OVDD
DGND
N/C
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