FIGURE 13. TRANSMITTER O
參數(shù)資料
型號： XR17V352IB113-F
廠商： Exar Corporation
文件頁數(shù)： 36/64頁
文件大小： 0K
描述： IC UART PCIE 256B DUAL 113FPBGA
產(chǎn)品培訓(xùn)模塊： PCIe UARTs
標(biāo)準(zhǔn)包裝： 260
特點： *
通道數(shù)： 2，DUART
FIFO's： 256 字節(jié)
規(guī)程： RS485
電源電壓： 3.3V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
安裝類型： 表面貼裝
封裝/外殼： 113-LFBGA
供應(yīng)商設(shè)備封裝： 113-FPBGA
包裝： 托盤
其它名稱： 1016-1471
XR17V352IB113-F-ND
FIGURE 13. TRANSMITTER OPERATION IN NON-FIFO MODE
Tr a n s m it
Ho ld in g
R egis t e r
( T HR)
T r an s m it S h if t R e gis t er ( T S R )
Da t a
By t e
L
S
B
M
S
B
T H R In te r r u p t ( IS R b it- 1 )
E nab led by I E R bit - 1
1 6X or 8X or 4X
Clo c k
XR17V352
41
REV. 1.0.3
HIGH PERFORMANCE DUAL PCI EXPRESS UART
3.6.3
Transmitter Operation in FIFO Mode
The host may fill the transmit FIFO with up to 256 bytes of transmit data. The THR empty flag (LSR bit [5]) is
set whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit [1])
when the amount of data in the FIFO falls below its programmed trigger level (see TXTRG register). The
transmit empty interrupt is enabled by IER bit [1]. The TSR flag (LSR bit [6]) is set when TSR becomes
completely empty. Furthermore, with the RS485 half-duplex direction control enabled (FCTR bit [5]=1) the
source of the transmit empty interrupt changes to TSR empty instead of THR empty. This is to ensure the
RTS# output is not changed until the last stop bit of the last character is shifted out.
3.6.4
Auto RS485 Operation
The auto RS485 half-duplex direction control changes the behavior of the transmitter when enabled by FCTR
bit [5]. It de-asserts RTS# or DTR# after a specified delay indicated in MSR[7:4] following the last stop bit of the
last character that has been transmitted. This helps in turning around the transceiver to receive the remote
station’s response. The delay optimizes the time needed for the last transmission to reach the farthest station
on a long cable network before switching off the line driver. This delay prevents undesirable line signal
disturbance that causes signal degradation. It also changes the transmitter empty interrupt to TSR empty
instead of THR empty.
FIGURE 14. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE
Transmit Data Shift Register
(TSR)
Transmit
Data Byte
THR Interrupt (ISR bit-1) falls
below Programmed Trigger
Level (TXTRG) and then
when becomes empty. FIFO
is Enabled by FCR bit-0=1
Transmit
FIFO
(256-Byte)
16X or 8X or 4X
Clock
Auto CTS Flow Control (CTS# pin)
Auto Software Flow Control
Flow Control Characters
(Xoff1/2 and Xon1/2 Reg.
相關(guān)PDF資料
PDF描述
XR17V354IB176-F IC UART PCIE 256B QUAD 176FPBGA
XR17V358IB176-F IC UART PCIE OCTAL 176FPBGA
XR19L200IL32-F IC UART/TXRX RS232 32QFN
XR19L202IL48-F IC UART/TXRX RS232 48QFN
XR19L210IL40-F IC UART/TXRX RS232 40QFN
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XR17V354 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE QUAD PCI-EXPRESS UART
XR17V354IB-0A-EVB 功能描述:界面開發(fā)工具 Eval Board for XR17V354IB-0A RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
XR17V354IB176-F 功能描述:UART 接口集成電路 4 Channel PCIe UART w/256 Byte FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR17V354IB-E4-EVB 功能描述:界面開發(fā)工具 Eval Board for XR17V354IB-E4 RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
XR17V354IB-E8-EVB 功能描述:界面開發(fā)工具 Eval Board for XR17V354IB-E8 RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*