參數(shù)資料
型號(hào)： XR17V354IB176-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 1/66頁(yè)
文件大?。?/td> 0K
描述： IC UART PCIE 256B QUAD 176FPBGA
產(chǎn)品培訓(xùn)模塊： PCIe UARTs
標(biāo)準(zhǔn)包裝： 160
特點(diǎn)： *
通道數(shù)： 4，QUART
FIFO's： 256 字節(jié)
規(guī)程： RS485
電源電壓： 3.3V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
安裝類型： 表面貼裝
封裝/外殼： 176-LFBGA
供應(yīng)商設(shè)備封裝： 176-FPBGA（13x13）
包裝： 托盤
其它名稱： 1016-1472
XR17V354IB176-F-ND
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com
XR17V354
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
APRIL 2012
REV. 1.0.3
GENERAL DESCRIPTION
The XR17V3541 (V354) is a single chip 4-channel
PCI Express (PCIe) UART (Universal Asynchronous
Receiver and Transmitter), optimized for higher
performance and lower power. The V354 serves as a
single lane PCIe bridge to 4 indepedent enhanced
16550 compatible UARTs. The V354 is compliant to
PCIe 2.0 Gen 1 (2.5GT/s).
In addition to the UART channels, the V354 has 16
multi-purpose I/Os (MPIOs), a 16-bit general purpose
counter/timer and a global interrupt status register to
optimize interrupt servicing.
Each UART of the V354 has many enhanced
features such as the 256-bytes TX and RX FIFOs,
programmable Fractional Baud Rate Generator,
Automatic Hardware or Software Flow Control, Auto
RS-485 Half-Duplex Direction Control, programmable
TX and RX FIFO Trigger Levels, TX and RX FIFO
Level Counters, infrared mode, and data rates up to
25Mbps. The V354 is available in a 176-pin FPBGA
package (13 x 13 mm).
NOTE 1: Covered by U.S. Patents #5,649,122, #6,754,839,
#6,865,626 and #6,947,999
APPLICATIONS
Next generation Point-of-Sale Systems
Remote Access Servers
Storage Network Management
Factory Automation and Process Control
Multi-port RS-232/RS-422/RS-485 Cards
FEATURES
Single 3.3V power supply
Internal buck regulator for 1.2V core
PCIe 2.0 Gen 1 compliant
x1 Link, dual simplex, 2.5Gbps in each direction
Expansion bus interface
EEPROM interface for configuration
Data read/write 32-bit operation
Global interrupt status register for all four UARTs
Up to 25 Mbps serial data rate
16 multi-purpose inputs/outputs (MPIOs)
16-bit general purpose timer/counter
Sleep mode with wake-up Indicator
Four independent UART channels controlled with
■
16550 compatible register Set
■
256-byte TX and RX FIFOs
■
Programmable TX and RX Trigger Levels
■
TX/RX FIFO Level Counters
■
Fractional baud rate generator
■
Automatic RTS/CTS or DTR/DSR hardware
flow control with programmable hysteresis
■
Automatic Xon/Xoff software flow control
■
RS-485 half duplex direction control output
with programmable turn-around delay
■
Multi-drop with Auto Address Detection
■
Infrared (IrDA 1.1) data encoder/decoder
Software compatible to XR17C15x, XR17D15x,
XR17V25x PCI UARTs
FIGURE 1. BLOCK DIAGRAM OF THE XR17V354
G loba l
C onfigur a tion
R eg ister s
C r ystal O s c/B u ffer
P C I L o cal
Bu s
In te r fa c e
C o nfigur a tion
Sp a c e
R eg ister s
- pur pos e
In puts /O utputs
16 - b it
Tim e r/C ounte r
UA RT Ch a n n e l 0
6 4 - b y te TX FIFO
6 4 - by te R X F IFO
BR G
IR
E NDE C
T X & RX
U ART
Re g s
UA RT Ch a n n e l 2
UA RT Ch a n n e l 3
UA RT Ch a n n e l 5
UA RT Ch a n n e l 6
UA RT Ch a n n e l 7
TM R C K
RX[7 :0 ]
T X [7 :0 ]
EE PRO M
In ter face
G loba l
C onfigur a tion
R eg ister s
G loba l
C onfigur a tion
R eg ister s
PCIe
In ter face
C o nfigur a tion
Sp a c e
R eg ister s
Mu lti-p u rp o s e
Inputs /O utputs
16 - b it
Tim e r/C ounte r
16 - b it
Tim e r/C ounte r
UA RT Ch a n n e l 0
6 4 - b y te TX FIFO
64-
BR G
IR
E NDE C
T X & RX
U ART
Re g s
UA RT Ch a n n e l 0
256-b yte T X F IF O
BR G
IR
E NDE C
TX & R X
U ART
Re g s
UA RT Ch a n n e l 1
UA RT Ch a n n e l 2
UA RT Ch a n n e l 3
TM R C K
R X [3 :0 ]
T X [3 :0 ]
R T S # [3 :0 ]
DT R # [3 :0 ]
C T S # [3 :0 ]
D S R # [3 :0 ]
D C D #[3 :0]
MP IO [1 5 :0 ]
R I#[3 :0]
EE PRO M
In ter face
EE PRO M
In ter face
256-b y te R X F IF O
E x pa ns ion
In te rfa c e
B uc k R e gula tor
125 M H z C lo ck
TX +
RX +
EE C K
EE D O
EE C S
EE D I
EN IR#
TX -
RX-
CL K +
CL K-
CL KR EQ #
PE R S T #
E N 485#
D [7:0]
SE L
IN T
MO D E
CL K
PR E S
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