參數(shù)資料
型號(hào): XR17V352IB113-F
廠商: Exar Corporation
文件頁(yè)數(shù): 22/64頁(yè)
文件大?。?/td> 0K
描述: IC UART PCIE 256B DUAL 113FPBGA
產(chǎn)品培訓(xùn)模塊: PCIe UARTs
標(biāo)準(zhǔn)包裝: 260
特點(diǎn): *
通道數(shù): 2,DUART
FIFO's: 256 字節(jié)
規(guī)程: RS485
電源電壓: 3.3V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 113-LFBGA
供應(yīng)商設(shè)備封裝: 113-FPBGA
包裝: 托盤
其它名稱: 1016-1471
XR17V352IB113-F-ND
PCI Bus
Data Bit-31
B7 B6 B5 B4 B3 B2 B1 B0
Receive Data Byte n+3
Receive Data Byte n+2
Receive Data Byte n+1
Receive Data Byte n+0
PCI Bus
Data Bit-0
Channel 0 to 1 Receive Data in 32-bit alignment through the Configuration Register Address
0x0100 and 0x0500
XR17V352
29
REV. 1.0.3
HIGH PERFORMANCE DUAL PCI EXPRESS UART
2.1.2
Special Rx FIFO Data Unloading at locations 0x0200 and 0x0600
The XR17V352 also provides the same RX FIFO data along with the LSR status information of each byte side-
by-side, at locations 0x0200 (channel 0) and 0x0600 (channel 1). The Status and Data bytes must be read in
16 or 32 bits format to maintain data integrity. The following tables show this clearly.
READ RX FIFO,
WITH LSR
ERRORS
BYTE 3
BYTE 2
BYTE 1
BYTE 0
Read n+0 to n+1
FIFO Data n+1
LSR n+1
FIFO Data n+0
LSR n+0
Read n+2 to n+3
FIFO Data n+3
LSR n+3
FIFO Data n+2
LSR n+2
Etc
PCI Bus
Data Bit-31
B7 B6 B5 B4 B3 B2 B1 B0
Receive Data Byte n+1
Line Status Register n+1
Receive Data Byte n+0
Line Status Register n+0
PCI Bus
Data Bit-0
Channel 0 to 1 Receive Data with Line Status Register in 32-bit alignment through the Configuration
Register Address 0x0200 and 0x0600
2.1.3
Tx FIFO Data Loading at locations 0x100 and 0x500
The TX FIFO data can be loaded 32 bits (4 bytes) at a time at memory locations 0x0100 (channel 0) and
0x0500 (channel 1).
WRITE TX FIFO
BYTE 3
BYTE 2
BYTE 1
BYTE 0
Write n+0 to n+3
FIFO Data n+3
FIFO Data n+2
FIFO Data n+1
FIFO Data n+0
Write n+4 to n+7
FIFO Data n+7
FIFO Data n+6
FIFO Data n+5
FIFO Data n+4
Etc.
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