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參數(shù)資料
| 型號： | XR16L651 |
| 廠商： | Exar Corporation |
| 英文描述： | 2.5V, 3.3V and 5V Low Power UART with 32-Byte FIFO(2.5V, 3.3V和5V 低功耗通用異步接收器/發(fā)送器（帶32字節(jié)先進先出）) |
| 中文描述： | 2.5V，3.3V與5V的低功耗的UART與32字節(jié)的FIFO（2.5伏，3.3伏和5V的低功耗通用異步接收器/發(fā)送器（帶32字節(jié)先進先出）） |
| 文件頁數(shù)： | 6/46頁 |
| 文件大小： | 516K |
| 代理商： | XR16L651 |
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XR16L651
2.5V, 3.3V AND 5V LOW POWER UART WITH 32-BYTE FIFO
REV. P1.0.0
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PRELIMINARY
6
PRODUCT DESCRIPTION
The XR16L651 (651) is industry first multi-voltage
UART that can operate at 2.5, 3.3 or 5V power sup-
plies. Its inputs are 5V tolerant to facilitate intercon-
nection to transceiver devices of RS-232, RS-422 or
RS-485. The 651 is software compatible to the indus-
try standad 16C550 with additional enhanced fea-
tures.
The 651 provides serial asynchronous receive data
synchronization, parallel-to-serial and serial-to-paral-
lel data conversions for both the transmitter and re-
ceiver sections. These functions are necessary for
converting the serial data stream into parallel data
that is required with digital data systems. Synchroni-
zation for the serial data stream is accomplished by
adding start and stops bits to the transmit data to
form a data character (character orientated protocol).
Data integrity is ensured by attaching a parity bit to
the data character. The parity bit is checked by the re-
ceiver for any transmission bit errors. The electronic
circuitry to provide all these functions is fairly complex
especially when manufactured on a single integrated
silicon chip. The XR16L651 represents such an inte-
gration with greatly enhanced features. The 651 is
fabricated with an advanced CMOS process.
The 651 supports standard 8-bit Intel, Motorola or PC
bus interfaces through 2 input selection pins. The In-
tel bus uses separate input/output read and write sig-
nals for all bus transactions while the Motorola bus
uses a read/write signal and chip select to conduct
the same transactions. The PC bus mode associates
with the PC ISA bus and follow the industry standard
PC definitions for COM 1-4 serial port addresses. The
651 includes on-board chip select decode logic and
selection for the proper interrupt request. This elimi-
nates the need for an external logic array device.
The 651 has 32-byte each of transmit and receive
FIFOs, automatic RTS/CTS hardware flow control
with hysteresis, automatic Xon/Xoff and special char-
acter software flow control, programmable transmit
and receive FIFO trigger levels, wireless infrared en-
coder and decoder (IrDA ver 1.0), programmable
baud rate generator with a prescaler of divide by 1 or
4, and data rate up to 1.0 Mbps at 16X sampling clock
rate.
The 651 is an upward solution that provides 32 bytes
of transmit and receive FIFO memory, instead of 16
bytes provided in the 16C550, or none in the 16C450.
The 651 is designed to work with high speed commu-
nication devices, that require fast data processing
time. Increased performance is realized in the 651 by
the larger transmit and receive FIFOs. This allows the
external processor to handle more networking tasks
within a given time. For example, the standard
ST16C550 with a 16 byte FIFO, unloads 16 bytes of
receive data in 1.53 ms (This example uses a charac-
ter length of 11 bits, including start/stop bits at
115.2Kbps). This means the external CPU will have
to service the receive FIFO at 1.53 ms intervals. How-
ever with the 32 byte FIFO in the 651, the data buffer
will not require unloading/loading for 3.05 ms. This in-
creases the service interval giving the external CPU
additional time for other applications and reducing the
overall UART interrupt servicing time. In addition, the
4 selectable levels of FIFO trigger interrupt and auto-
matic hardware/software flow control is uniquely pro-
vided for maximum data throughput performance es-
pecially when operating in a multi-channel environ-
ment. The combination of the above greatly reduces
the bandwidth requirement of the external controlling
CPU, increases performance, and reduces power
consumption.
The rich feature set of the 651 is available through in-
ternal registers. Automatic hardware/software flow
control, selectable transmit and receive FIFO trigger
levels, selectable TX and RX baud rates, infrared en-
coder/decoder interface, modem interface controls,
and a sleep mode are all standard features. In the PC
mode, two tri-state interrupt lines (IRQB and IRQC)
and one selectable open source interrupt output
(IRQA) are available. The open source interrupt
scheme allows multiple interrupts to be combined in a
“wire-OR” operation, thus reducing the number of in-
terrupt lines in larger systems. Following a power on
reset or an external reset, the 651 is software com-
patible with previous generation of UARTs, 16C450,
16C550 and ST16C650A.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR16L651CM | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 5.5V UART WITH 32-BYTE FIFO |
| XR16L651CM-0A-EVB | 功能描述:UART 接口集成電路 Supports L651 48 ld TQFP, ISA Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16L651CM-F | 功能描述:UART 接口集成電路 UARTW/32BYTEFIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16L651CMTR-F | 制造商:Exar Corporation 功能描述:UART 1-CH 32Byte FIFO 2.5V/3.3V/5V 48-Pin TQFP T/R 制造商:Exar Corporation 功能描述:XR16L651CMTR-F |
| XR16L651IM | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
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