參數(shù)資料
型號： XR16L651
廠商： Exar Corporation
英文描述： 2.5V, 3.3V and 5V Low Power UART with 32-Byte FIFO(2.5V, 3.3V和5V 低功耗通用異步接收器/發(fā)送器（帶32字節(jié)先進先出）)
中文描述： 2.5V，3.3V與5V的低功耗的UART與32字節(jié)的FIFO（2.5伏，3.3伏和5V的低功耗通用異步接收器/發(fā)送器（帶32字節(jié)先進先出））
文件頁數(shù)： 28/46頁
文件大小： 516K
代理商： XR16L651
XR16L651
2.5V, 3.3V AND 5V LOW POWER UART WITH 32-BYTE FIFO
REV. P1.0.0
á
PRELIMINARY
28
until the RX input returns to the idle condition,
“mark” or logic 1.
LSR[5]: Transmit Holding Register Empty Flag
This bit is the Transmit Holding Register Empty indi-
cator. This bit indicates that the transmitter is ready to
accept a new character for transmission. In addition,
this bit causes the UART to issue an interrupt to the
host when the THR interrupt enable is set. The THR
bit is set to a logic 1 when the last data byte is trans-
ferred from the transmit holding register to the trans-
mit shift register. The bit is reset to logic 0 concurrent-
ly with the data loading to the transmit holding regis-
ter by the host. In the FIFO mode this bit is set when
the transmit FIFO is empty, it is cleared when the
transmit FIFO contains at least 1 byte.
LSR[6]: Transmit Shift Register Empty Flag
This bit is the Transmit Shift Register Empty indicator.
This bit is set to a logic 1 whenever the transmitter
goes idle. It is set to logic 0 whenever either the THR
or TSR contains a data character. In the FIFO mode
this bit is set to one whenever the transmit FIFO and
transmit shift register are both empty.
LSR[7]: Receive FIFO Data Error Flag
Logic 0 = No FIFO error. (default)
Logic 1 = A global indicator for the sum of all error
bits in the RX FIFO. At least one parity error, fram-
ing error or break indication is in the FIFO data.
This bit clears when there is no more error(s) in the
FIFO.
6.9
E
XTRA
F
EATURE
R
EGISTER
(XFR) - W
RITE
O
NLY
This register provides additonal features and controls
to the XR16L651 UART.
XFR [0]: Half-duplex Infrared Mode Enable
When infrared mode is enabled, MCR bit-6=1, this bit
selects the infrared mode to operate in normal full-du-
plex or half-duplex mode. This half-duplex mode fea-
ture is very desirable when user does not want to
“see” his own sending data that are echoed through
the reflection of lights.
Logic 0 = Disable. The receiver is active during data
transmission.
Logic 1 = Enabled half-duplex operation. The infra-
red receiver is disabled during data transmission.
XFR [1]: Invert Received Infrared Input Signal
This bit controls the input polarity of the infrared data.
Logic 0 = Infrared data input idles at logic 0.
(default)
Logic 1 = Infrared data idles at logic 1, pulses low.
XFR [2]: Auto RS485 Enable
This bit enables the auto RS485 direction control fea-
ture for half-duplex operation with RS-485 transceiv-
er. The feature should only be enabled when normal
RTS# output and auto RTS flow control are not in
used.
Logic 0 = Disable the auto RS485 direction control
function. This allows normal RTS# output or auto
RTS flow control operation.
Logic 1 = Enable the auto RS485 direction function.
The RTS# output will automatically change its logic
state to control the RS-485 transceiver from send-
ing and receiving. Also see XFR bit-5 and section
5.6.3.
XFR [3]: LSR Bad Data Interrupt Operation
When the LSR interrupt is enabled, IER bit-2=1, this
bit selects when the interrupt pin (INT) will report re-
ceived character error: parity, framing or break. Use
this feature only if application needs immediate
knowledge when a bad character is received.
Logic 0 = Received data error interrupt (LSR inter-
rupt) will be generated when the bad character is
available for reading from the FIFO. This is compat-
ible to industry standard 16C550 operation.
Logic 1 = Received data error interrupt (LSR inter-
rupt) is generated immediately upon receipt of the
bad character. It will be reset when LSR is read. If
user does not read the bad character out, another
bad character interrupt is generated when it’s avail-
able for reading from the FIFO.
XFR [4]: XonAny Enable
This bit enables and disables the Xon-Any function
when Xon/Xoff software flow control is enabled.
Logic 0 = Disable the Xon-Any function.
Logic 1 = Enable the Xon-Any function. The
receiver will use any received character as an Xon
character and resume data transmission.
XFR [5]: Invert Auto RS-485 Control Output
When Auto RS485 feature is enabled, XFR bit-2=1,
RTS# output automatically changes its logic state to
control the RS-485 transceiver.
Logic 0 = During auto RS-485, RTS# control output
signal to the transceiver is logic 1 for transmit and
logic 0 for receive.
Logic 1 = The RTS# output control signal to the
transceiver is logic 0 for transmit and logic 1 for
receive. User must assert RTS# for operation to
take effect.
XFR [7:6]
Not used, reserved.
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