參數(shù)資料
型號: XR16L651
廠商: Exar Corporation
英文描述: 2.5V, 3.3V and 5V Low Power UART with 32-Byte FIFO(2.5V, 3.3V和5V 低功耗通用異步接收器/發(fā)送器(帶32字節(jié)先進(jìn)先出))
中文描述: 2.5V,3.3V與5V的低功耗的UART與32字節(jié)的FIFO(2.5伏,3.3伏和5V的低功耗通用異步接收器/發(fā)送器(帶32字節(jié)先進(jìn)先出))
文件頁數(shù): 3/46頁
文件大小: 516K
代理商: XR16L651
á
XR16L651
2.5V, 3.3 AND 5V LOW POWER UART WITH 32-BYTE FIFO
PRELIMINARY
REV. P1.0.0
3
PIN DESCRIPTIONS
N
OTE
:
Pin type: I=Input, O=Output, IO= Input/output,
OD=Output Open Drain.
N
AME
P
IN
#
T
YPE
D
ESCRIPTION
16 (Intel) or 68 (Motorola) MODE DATA BUS INTERFACE. The PCMODE# pin is connected to VCC.
A2-A0
26,27,28
I
Address data lines [2:0]. A0:A2 selects internal UART’s configuration registers.
D7:D0
4,3,2,48-44
IO
Data bus lines [7:0] (bidirectional).
IOR#
19
I
Input/Output Read (active low). When IM# pin is at logic 0, it selects Intel bus
interface and this input is read strobe (active low). The falling edge instigates
an internal read cycle and retrieves the data byte from an internal register
pointed by the address lines [A2:A0], places it on the data bus to allow the
host processor to read it on the leading edge. When IM# pin is at logic 1, it
selects Motorola bus interface and the IOR# input is not used and it should be
connected to GND to minimize supply curent. Its function is the same as IOR,
except it is active low. Either an active IOR# or IOR is required to transfer data
from 651 to CPU during a read operation.
IOR
20
Input/Output Read (active high). Same as IOR# but active high. When IM#
pin is at logic 1 for Motorola bus mode, this pin is not used and should be con-
nected to GND to minimize supply curent.
IOW#
(R/W#)
16
I
When IM# pin is at logic 0, it selects Intel bus interface and this input
becomes write strobe (active low). The falling edge instigates the internal
write cycle and the trailing edge transfers the data byte on the data bus to an
internal register pointed by the address lines [A2:A0]. Its function is the same
as IOW, except it is active low. Either an active IOW# or IOW is required to
transfer data from 651 to the Intel type CPU during a write operation. When
IM# pin is at logic 1, it selects Motorola bus interface and this input becomes
R/W# signal for read (logic 1) and write (logic 0).
IOW
17
Input/Output Write. Same as IOW# but active high. When IM# pin is at logic 1
for Motorola bus mode, this pin must be connected to GND to allow IOW#
input to function correctly.
CS0
9
I
Chip Select 0 input (active high). This input selects the XR16L651 device. If
CS1 or CS2# is used as the chip select then this pin must be connected to
VCC.
CS1
10
Chip Select 1 input (active high). This input selects the XR16L651 device. If
CS0 or CS2# is used as the chip select then this pin must be connected to
VCC.
CS2#
11
Chip Select 2 input (active low). This input selects the XR16L651 device. If
CS0 or CS1 is used as the chip select then this pin must be connected to
GND.
INT
(INT#)
30
O
Interrupt Output. This output becomes active whenever the transmitter,
receiver, line and/or modem status register has an active condition. See inter-
rupt section for more detail. When IM# pin is at logic 0 (Intel bus mode), this
interrupt output may be set to normal active high or active high open source to
provide wire-OR capability by connecting a 1k to 10k ohms resistor between
this pin and ground. When IM# pin is at logic 1 (Motorola bus mode), this
interrupt output becomes an open drain, active low output. It requires an
external pull-up resistor of 1K-10K ohms to operate properly. The output may
be wire-OR’ed with other devices in the system to form a single interrupt
request to the host processor and have the software driver poll all devices to
determine the interrupting condition(s).
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