參數(shù)資料
型號(hào)： XR16L651
廠商： Exar Corporation
英文描述： 2.5V, 3.3V and 5V Low Power UART with 32-Byte FIFO(2.5V, 3.3V和5V 低功耗通用異步接收器/發(fā)送器（帶32字節(jié)先進(jìn)先出）)
中文描述： 2.5V，3.3V與5V的低功耗的UART與32字節(jié)的FIFO（2.5伏，3.3伏和5V的低功耗通用異步接收器/發(fā)送器（帶32字節(jié)先進(jìn)先出））
文件頁(yè)數(shù)： 23/46頁(yè)
文件大?。?/td> 516K
代理商： XR16L651
á
XR16L651
2.5V, 3.3 AND 5V LOW POWER UART WITH 32-BYTE FIFO
PRELIMINARY
REV. P1.0.0
23
register to the receive FIFO. It is reset when the
FIFO is empty.
6.3.2
IER versus Receive/Transmit FIFO Polled
Mode Operation
When FCR BIT-0 equals a logic 1 for FIFO enable; re-
setting IER bits 0-3 enables the XR16L651 in the
FIFO polled mode of operation. Since the receiver
and transmitter have separate bits in the LSR either
or both can be used in the polled mode by selecting
respective transmit or receive control bit(s).
A.
LSR BIT-0 indicates there is data in RHR
or
RX
FIFO.
B.
LSR BIT 1-4 provides the type of receive data er-
rors encountered for the data byte in RHR, if any.
C.
LSR BIT-5 indicates THR is empty.
D.
LSR BIT-6 indicates when both the transmit FIFO
and TSR are empty.
E.
LSR BIT-7 indicates the wire-OR function of all
errors in the RX FIFO.
IER[0]: RHR Interrupt Enable
The receive data ready interrupt will be issued when
RHR has a data character in the non-FIFO mode
or
when the receive FIFO has reached the programmed
trigger level in the FIFO mode.
Logic 0 = Disable the receive data ready interrupt.
(default)
Logic 1 = Enable the receiver data ready interrupt.
IER[1]: THR Interrupt Enable
This bit enables the Transmit Ready interrupt which is
issued whenever the THR becomes empty or when
data in the FIFO falls below the programmed trigger
level.
Logic 0 = Disable Transmit Holding Register empty in-
terrupt. (default)
Logic 1 = Enable Transmit Holding Register empty in-
terrupt.
IER[2]: Receive Line Status Interrupt Enable
Any change of state of the LSR register bits 1,2,3 or 4
will generate an interrupt to inform the host controller
about the error status of the current data byte in
FIFO.
Logic 0 = Disable the receiver line status interrupt.
(default)
Logic 1 = Enable the receiver line status interrupt.
IER[3]: Modem Status Interrupt Enable
Logic 0 = Disable the modem status register interrupt.
(default)
Logic 1 = Enable the modem status register interrupt.
IER[4]: Sleep Mode Enable (requires EFR bit-4 =
1)
Logic 0 = Disable Sleep Mode (default).
Logic 1 = Enable Sleep Mode. See Sleep Mode sec-
tion for further details.
IER[5]: Xoff Interrupt Enable (requires EFR bit-
4=1)
Logic 0 = Disable the software flow control, receive
Xoff interrupt. (default)
Logic 1 = Enable the software flow control, receive
Xoff interrupt. See Software Flow Control section for
details.
IER[6]: RTS# Output Interrupt Enable (requires
EFR bit-4=1)
Logic 0 = Disable the RTS# interrupt. (default ).
Logic 1 = Enable the RTS# interrupt. The UART is-
sues an interrupt when the RTS# pin makes a transi-
tion.
IER[7]: CTS# Input Interrupt Enable (requires EFR
bit-4=1)
Logic 0 = Disable the CTS# interrupt. (default).
Logic 1 = Enable the CTS# interrupt. The UART is-
sues an interrupt when CTS# pin makes a transition.
6.4
I
NTERRUPT
S
TATUS
R
EGISTER
(ISR)
The UART provides multiple levels of prioritized inter-
rupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with
six interrupt status bits. Performing a read cycle on
the ISR will give the user the current highest pending
interrupt level to be serviced, others queue up for next
service. No other interrupts are acknowledged until
the pending interrupt is serviced. The Interrupt
Source Table, Table 9, shows the data values (bit 0-5)
for the six prioritized interrupt levels and the interrupt
sources associated with each of these interrupt lev-
els.
6.4.1
Interrupt Generation:
LSR is by any of the LSR bits 1, 2, 3 and 4.
RXRDY is by RX trigger level.
RXRDY Time-out is by the a 4-char plus 12 bits
delay timer if data doesn’t reach FIFO trigger level.
TXRDY is by LSR bit-5 (or bit-6 in auto RS485 con-
trol).
MSR is by any of the MSR bits, 0, 1, 2 and 3.
Receive Xoff/Special character is by detection of a
Xoff or Special character.
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