參數(shù)資料
型號(hào): XR16C864
廠商: Exar Corporation
元件分類: 通用總線功能
英文描述: Quad UART with RX/TX FIFO Counters and 128-byte FIFO(四通用異步接收器/發(fā)送器(帶RX/TX 先進(jìn)先出計(jì)數(shù)器和128字節(jié)先進(jìn)先出))
中文描述: 四路與異步接收/發(fā)送FIFO的計(jì)數(shù)器和128字節(jié)的FIFO(四通用異步接收器/發(fā)送器(帶了Rx / Tx先進(jìn)先出計(jì)數(shù)器和128字節(jié)先進(jìn)先出))
文件頁數(shù): 4/46頁
文件大小: 381K
代理商: XR16C864
XR16C864
4
Rev. 1.10
SYMBOL DESCRIPTION
Symbol
Pin
100
Signal
type
Pin Description
16/-68
36
I
16/68 Interface Type Select (input with internal pull-up). - This input provides
the 16 (Intel) or 68 (Motorola) bus interface type select. The functions of -IOR,
-IOW, INT A-D, and -CS A-D are re-assigned with the logical state of this pin.
When this pin is a logic 1, the 16 mode interface is selected. When this pin
is a logic 0, the 68 mode interface is selected. When this pin is a logic 0, -
IOW is re-assigned to R/-W, RESET is re-assigned to -RESET, -IOR is not
used, and INT A-D(s) are connected in a WIRE-OR” configuration. The
WIRE-OR outputs are connected internally to the open source IRQ signal
output.
A0
39
I
Address-0 Select Bit. Internal registers address selection in 16 and 68
modes.
A1
38
I
Address-1 Select Bit. Internal registers address selection in 16 and 68
modes.
A2
37
I
Address-2 Select Bit. - Internal registers address selection in 16 and 68
modes.
CLKSEL
35
I
Clock Select. - The pre-scaleable clock is selected by this pin. The div-by-
1 clock is selected when CLKSEL is a logic 1 (connected to VCC) or the div-
by-4 is selected when CLKSEL is a logic 0 (connected to GND). MCR bit-
7 can override the state of this pin following reset or initialization (see MCR
bit-7).
-CSRDY
76
I
Control Status Ready (active low) - The Contents of the FIFORDY Register
is read when this pin is a logic 0. However it should be noted, D0-D3 will
contain the inverted logic states of TXRDY A-D, and D4-D7 the logic states
(un-inverted) of RXRDY A-D.
D0-D2
D3-D7
88-90
91-95
I/O
Data Bus (Bi-directional) - These pins are the eight bit, three state data bus
for transferring information to or from the controlling CPU. D0 is the least
significant bit and the first data bit in a transmit or receive serial data stream.
TC
54
I
Terminal Count. A high pulse terminates a DMA transaction.
AEN
27
I
Address Enable. A high at this input indicates valid DMA cycle. See DACK
pins for DMA cycle description.
sa
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XR16C864CQ-0B-EB 功能描述:界面開發(fā)工具 Eval Board for XR16C864CQ Series RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
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