
XR16C864
16
Rev. 1.10
C1
22pF
C2
33pF
X1
1.8432 MHz
X
X
Figure 4, Crystal oscillator connection
Hardware/Software and Timeout Interrupts
Three special interrupts have been added to monitor the
hardware and software flow control. The interrupts are
enabled by IER bits 5-7. Care must be taken when
handling these interrupts. Following a reset the trans-
mitter interrupt is enabled, the 864 will issue an
interrupt to indicate that transmit holding register is
empty. This interrupt must be serviced prior to con-
tinuing operations. The ISR register provides the current
singular highest priority interrupt only. It could be noted
that CTS and RTS interrupts have lowest interrupt
priority. A condition can exist where a higher priority
interrupt may mask the lower priority CTS/RTS
interrupt(s). Only after servicing the higher pending
interrupt will the lower priority CTS/ RTS interrupt(s) be
reflected in the status register. Servicing the interrupt
without investigating further interrupt conditions can
result in data errors.
When two interrupt conditions have the same priority,
it is important to service these interrupts correctly.
Receive Data Ready and Receive Time Out have the
same interrupt priority (when enabled by IER bit-3).
The receiver issues an interrupt after the number of
characters have reached the programmed trigger
level. In this case the 864 FIFO may hold more
characters than the programmed trigger level. Follow-
ing the removal of a data byte, the user should recheck
LSR bit-0 for additional characters. A Receive Time
Out will not occur if the receive FIFO is empty. The
time out counter is reset at the center of each stop bit
received or each time the receive holding register
(RHR) is read. The actual time out value is T (
T
ime out
length in bits) = 4 X P (
P
rogrammed word length) + 12.
To convert the time out value to a character value, the
user has to consider the complete word length, includ-
ing data information length, start bit, parity bit, and the
size of stop bit, i.e., 1, 1.5, or 2 bit times.
Example -A: If the user programs a word length of 7,
with no parity and one stop bit, the time out will be:
T = 4 X 7( programmed word length) +12 = 40 bit times.
The character time will be equal to 40 / 9 = 4.4
characters, or as shown in the fully worked out ex-
ample: T = [(programmed word length = 7) + (stop bit
= 1) + (start bit = 1) = 9]. 40 (bit times divided by 9) =
4.4 characters.
Example -B: If the user programs the word length = 7,
with parity and one stop bit, the time out will be:
T = 4 X 7(programmed word length) + 12 = 40 bit times.
Character time = 40 / 10 [ (programmed word length =
7) + (parity = 1) + (stop bit = 1) + (start bit = 1) = 4
characters.
In the 16 mode, the system/board designer can option-
ally provide software controlled three state interrupt
operation. This is accomplished by INTSEL and MCR
bit-3. When INTSEL interface pin is left open or made a
logic 0, MCR bit-3 controls the three state interrupt
outputs, INT A-D. When INTSEL is a logic 1, MCR bit-
3 has no effect on the INT A-D outputs and the package
operates with interrupt outputs enabled continuously.
Programmable Baud Rate Generator
The 864 supports high speed modem technologies
that have increased input data rates by employing
data compression schemes. For example a 33.6Kbps
modem that employs data compression may require a
115.2Kbps input data rate. A 128.0Kbps ISDN modem
that supports data compression may need an input
data rate of 460.8Kbps. The 864 can support a stan-
dard data rate of 921.6Kbps.