參數(shù)資料
型號(hào)： XR16C864
廠商： Exar Corporation
元件分類： 通用總線功能
英文描述： Quad UART with RX/TX FIFO Counters and 128-byte FIFO(四通用異步接收器/發(fā)送器（帶RX/TX 先進(jìn)先出計(jì)數(shù)器和128字節(jié)先進(jìn)先出）)
中文描述： 四路與異步接收/發(fā)送FIFO的計(jì)數(shù)器和128字節(jié)的FIFO（四通用異步接收器/發(fā)送器（帶了Rx / Tx先進(jìn)先出計(jì)數(shù)器和128字節(jié)先進(jìn)先出））
文件頁(yè)數(shù)： 23/46頁(yè)
文件大?。?/td> 381K
代理商： XR16C864
XR16C864
23
Rev. 1.10
Transmit (THR) and Receive (RHR) Holding Regis-
ters
The serial transmitter section consists of an 8-bit
Transmit Hold Register (THR) and Transmit Shift
Register (TSR). The status of the THR is provided in
the Line Status Register (LSR). Writing to the THR
transfers the contents of the data bus (D7-D0) to the
THR, providing that the THR or TSR is empty. The
THR empty flag in the LSR register will be set to a logic
1 when the transmitter is empty or when data is
transferred to the TSR. Note that a write operation can
be performed when the transmit holding register
empty flag is set (logic 0 = at least one byte in FIFO/
THR, logic 1= FIFO/THR empty).
The serial receive section also contains an 8-bit
Receive Holding Register, RHR. Receive data is
removed from the 864 and receive FIFO by reading
the RHR register. The receive section provides a
mechanism to prevent false starts. On the falling edge
of a start or false start bit, an internal receiver counter
starts counting clocks at 16x clock rate. After 7 1/2
clocks the start bit time should be shifted to the center
of the start bit. At this time the start bit is sampled and
if it is still a logic 0 it is validated. Evaluating the start
bit in this manner prevents the receiver from assem-
bling a false character. Receiver status codes will be
posted in the LSR.
Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) masks the inter-
rupts from receiver ready, transmitter empty, line
status and modem status registers. These interrupts
would normally be seen on the INT A-D output pins in
the 16 mode, or on WIRE-OR IRQ output pin, in the 68
mode.
IER Vs Receive FIFO Interrupt Mode Operation
When the receive FIFO (FCR BIT-0 = a logic 1) and
receive interrupts (IER BIT-0 = logic 1) are enabled,
the receive interrupts and register status will reflect
the following:
A) The receive data available interrupts are issued to
the external CPU when the FIFO has reached the
programmed trigger level. It will be cleared when the
FIFO drops below the programmed trigger level.
B) FIFO status will also be reflected in the user
accessible ISR register when the FIFO trigger level is
reached. Both the ISR register status bit and the
interrupt will be cleared when the FIFO drops below
the trigger level.
C) The data ready bit (LSR BIT-0) is set as soon as a
character is transferred from the shift register to the
receive FIFO. It is reset when the FIFO is empty.
IER Vs Receive/Transmit FIFO Polled Mode Op-
eration
When FCR BIT-0 equals a logic 1; resetting IER bits
0-3 enables the 864 in the FIFO polled mode of
operation. Since the receiver and transmitter have
separate bits in the LSR either or both can be used in
the polled mode by selecting respective transmit or
receive control bit(s).
A) LSR BIT-0 will be a logic 1 as long as there is one
byte in the receive FIFO.
B) LSR BIT 1-4 will provide the type of receive errors or
a receive break encountered, if any.
C) LSR BIT-5 will indicate when the transmit FIFO is
empty.
D) LSR BIT-6 will indicate when both the transmit
FIFO and transmit shift register are empty.
E) LSR BIT-7 will indicate any FIFO data errors.
IER BIT-0:
This interrupt will be issued when the FIFO has
reached the programmed trigger level or is cleared
when the FIFO drops below the trigger level in the
FIFO mode of operation.
Logic 0 = Disable the receiver ready interrupt. (normal
default condition)
Logic 1 = Enable the receiver ready interrupt.
IER BIT-1:
This interrupt will be issued whenever the THR is empty
(if FIFO is not enabled) or when the FIFO drops below
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參數(shù)描述
XR16C864CQ 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述:
XR16C864CQ-0A-EVB 功能描述:UART 接口集成電路 Supports C864 100 ld QFP, ISA Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR16C864CQ-0B-EB 功能描述:界面開發(fā)工具 Eval Board for XR16C864CQ Series RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
XR16C864CQ-F 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR16C864CQTR-F 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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