參數(shù)資料
型號: XR16C864
廠商: Exar Corporation
元件分類: 通用總線功能
英文描述: Quad UART with RX/TX FIFO Counters and 128-byte FIFO(四通用異步接收器/發(fā)送器(帶RX/TX 先進先出計數(shù)器和128字節(jié)先進先出))
中文描述: 四路與異步接收/發(fā)送FIFO的計數(shù)器和128字節(jié)的FIFO(四通用異步接收器/發(fā)送器(帶了Rx / Tx先進先出計數(shù)器和128字節(jié)先進先出))
文件頁數(shù): 31/46頁
文件大小: 381K
代理商: XR16C864
XR16C864
31
Rev. 1.10
to the programmed trigger level and -RTS will go to a
logic 1 at the next trigger level. -RTS will return to a logic
0 when data is unloaded below the programmed level
(See FCTR bits 1 and 0). The state of this register bit
changes with the status of the hardware flow control.
-RTS functions normally when hardware flow control is
disabled.
0 = Automatic RTS flow control is disabled. (normal
default condition)
1 = Enable Automatic RTS flow control.
EFR bit-7:
Automatic CTS Flow Control.
Logic 0 = Automatic CTS flow control is disabled.
(normal default condition)
Logic 1 = Enable Automatic CTS flow control. Transmis-
sion will stop when -CTS goes to a logical 1. Transmis-
sion will resume when the -CTS pin returns to a logical
0.
FIFO READY REGISTER
The FIFO Ready register provides the real time status
of the transmit and receive FIFO’s. Each TX and RX
channel (A-D) has its own 128 byte FIFO. When any of
the eight TX/RX FIFO’s become full, a bit associated
with its TX/RX function and channel A-D is set in the
FIFO status register. This read-only register can be
accessed when -CSRDY is low.
FIFO channel A-D RDY Bit 0-3:
0 = In the DMA mode (FCR bit-3 = 1), the transmit FIFO
A-D associated with this bit is full. This channel will not
accept any more transmit data. In the non-DMA mode
(FCR bit-3 = 0), this means there is at least one byte in
FIFO.
1 = In the DMA mode, one or more empty locations exist
in the FIFO. In the non-DMA mode, FIFO is empty.
FIFORdy Bit 4-7:
0 = In the DMA mode, the receive FIFO is above the
programmed trigger level or time-out has occurred. In
the non-DMA mode, at least one byte in FIFO.
1 = In both DMA and non-DMA modes, receive FIFO is
empty.
Table 6, SOFTWARE FLOW CONTROL FUNCTIONS
Bit-3
Bit-2
Bit-1
Bit-0
TX, RX software flow controls
0
1
0
1
X
X
X
1
0
0
1
1
X
X
X
0
X
X
X
X
0
1
0
1
X
X
X
X
0
0
1
1
No transmit flow control
Transmit Xon1/Xoff1
Transmit Xon2/Xoff2
Transmit Xon1 and Xon2/Xoff1 and Xoff2
No receive flow control
Receiver compares Xon1/Xoff1
Receiver compares Xon2/Xoff2
Transmit Xon1/ Xoff1.
Receiver compares Xon1 or Xon2,
Xoff1 or Xoff2
Transmit Xon2/Xoff2
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
Transmit Xon1 and Xon2/Xoff1 and Xoff2
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
No transmit flow control
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
0
1
1
1
1
1
1
1
0
0
1
1
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