參數(shù)資料
型號(hào): XR16C864
廠商: Exar Corporation
元件分類: 通用總線功能
英文描述: Quad UART with RX/TX FIFO Counters and 128-byte FIFO(四通用異步接收器/發(fā)送器(帶RX/TX 先進(jìn)先出計(jì)數(shù)器和128字節(jié)先進(jìn)先出))
中文描述: 四路與異步接收/發(fā)送FIFO的計(jì)數(shù)器和128字節(jié)的FIFO(四通用異步接收器/發(fā)送器(帶了Rx / Tx先進(jìn)先出計(jì)數(shù)器和128字節(jié)先進(jìn)先出))
文件頁(yè)數(shù): 25/46頁(yè)
文件大小: 381K
代理商: XR16C864
XR16C864
25
Rev. 1.10
disabled, FCR bit-0 = logic 0) or in the FIFO mode
(FIFO’s enabled, FCR bit-0 = logic 1, FCR bit-3 = logic
0) and when there are no characters in the transmit
FIFO or transmit holding register, the -TXRDY pin will
be a logic 0. Once active the -TXRDY pin will go to a
logic 1 after the first character is loaded into the
transmit holding register.
Receive operation in mode “0”:
When the 864 is in mode “0” (FCR bit-0 = logic 0) or
in the FIFO mode (FCR bit-0 = logic 1, FCR bit-3 =
logic 0) and there is at least one character in the
receive FIFO, the -RXRDY pin will be a logic 0. Once
active the -RXRDY pin will go to a logic 1 when there
are no more characters in the receiver.
Transmit operation in mode “1”:
When the 864 is in FIFO mode ( FCR bit-0 = logic 1,
FCR bit-3 = logic 1 ), the -TXRDY pin will be a logic 1
when the transmit FIFO is completely full. It will be a
logic 0 if one or more FIFO locations are empty.
Receive operation in mode “1”:
When the 864 is in FIFO mode (FCR bit-0 = logic 1,
FCR bit-3 = logic 1) and the trigger level has been
reached, or a Receive Time Out has occurred, the -
RXRDY pin will go to a logic 0. Once activated, it will
go to a logic 1 after there are no more characters in the
FIFO.
FCR BIT 4-5: (logic 0 or cleared is the default condi-
tion, TX trigger level = none)
The XR16C864 provide user selectable trigger levels,
The FCTR Bits 4-5 selects one of the following tables.
These bits are used to set the trigger level for the
transmit FIFO interrupt. The XR16C864 will issue a
transmit empty interrupt when number of characters in
FIFO drops below the selected trigger level. The bit 5
and bit 4 shown in the tables are the bits 5 and 4 of the
FCR register.
TRIGGER TABLE-A (Transmit)
“Default setting after reset ST16C550 mode”
BIT-5
BIT-4
FIFO trigger level
X
X
None
TRIGGER TABLE-B (Transmit)
BIT-5
BIT-4
FIFO trigger level
0
0
1
1
0
1
0
1
16
8
24
30
TRIGGER TABLE-C (Transmit)
BIT-5
BIT-4
FIFO trigger level
0
0
1
1
0
1
0
1
8
16
32
56
TRIGGER TABLE-D (Transmit)
For this setting, set FCTR bit-7 to "1" and program the
TRG register (in the Enhanced Register Set) with the
required trigger level. In this case, FCR bits 4 and 5 do
not control the TX FIFO trigger level.
TRG
BITS 7 to 0
FIFO trigger level
0xXX
User programmable
Trigger evels
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