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參數(shù)資料
| 型號(hào)： | XCCACE256-I |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 63/69頁(yè) |
| 文件大小： | 0K |
| 描述： | IC 256MBIT ACE FLASH CARD |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 存儲(chǔ)容量： | 256Mb |
| 存儲(chǔ)器類(lèi)型： | FLASH |
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System ACE CompactFlash Solution
66
DS080 (v3.0) April 7, 2014
Product Specification
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
POR_RESET(2)
72
IN
VCCH
Int. Pull-down
Power-on-reset bypass input; can be used in
conjunction with POR_BYPASS to bypass the
internal POR circuit in favor of using an external
board-level POR circuit; all internal circuitry is reset
when POR_BYPASS = 1 and POR_RESET = 1;
The POR_RESET pulse duration should be at least
1 microsecond long.
POR_TEST
74
OUT2
VCCH
N/A
Power-on-reset test output; this pin should be a true
No Connect on the board (see Table 40, page 68)
but is listed here for informational purposes.
POR_TEST is Low during power up and when
POR_BYPASS and POR_RESET are asserted
High (causing a device reset). After power up is
complete, POR_TEST is High when POR_BYPASS
is Low, or when POR_BYPASS is High and
POR_RESET is Low. An internal timer circuit in the
POR component determines when to release
POR_TEST after power reaches the ON threshold.
Notes:
1.
JTAG 1149.1 requires a pull-up resistor on potentially undriven TDO/TMS signals.
2.
If not using the RESET signal prior to CFGJTAG configuration, ensure that the VCCH and VCCL are brought all the way back to 0V
when power-cycling the board. Failure to do this, could cause the Power-On-Reset (POR) circuitry to operate incorrectly.
Table 38: System ACE CF Controller Pin Table (IN = input, OUT2 = 2-State Output, OUT3 = 3-State Output)
Pin Name
Pin #
I/O Type
I/O Supply Rail
Termination
Description
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