參數(shù)資料
型號(hào): XCCACE256-I
廠商: Xilinx Inc
文件頁數(shù): 11/69頁
文件大?。?/td> 0K
描述: IC 256MBIT ACE FLASH CARD
標(biāo)準(zhǔn)包裝: 1
存儲(chǔ)容量: 256Mb
存儲(chǔ)器類型: FLASH
System ACE CompactFlash Solution
DS080 (v3.0) April 7, 2014
19
Product Specification
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Interrupt Timing
The interrupt request and clearing cycles are shown in
Figure 15. In Figure 15, the interrupt request (MPIRQ =
HIGH) occurs sometime before Cycle 0. The interrupt
request is cleared by performing a single MPU write cycle
that sets RESETIRQ = 1 (bit number 11) in the CONTROL-
REG(15:0) register (BYTE address 0x19 or WORD address
0x0C).
The MPU interrupt request line (MPIRQ) remains active
HIGH until the RESETIRQ bit is set. The MPIRQ line
becomes inactive LOW two cycles after the completion of
the RESETIRQ write cycle (Cycle 4). For subsequent MPU
interrupt requests to be enabled, the RESETIRQ bit must be
reset and one of the three IRQ enable bits (DATABUFRDY-
IRQ, ERRORIRQ, and/or CFGDONEIRQ) in the CON-
TROLREG register should be set.
Figure 15: Interrupt Request Timing
0ns
50ns
100ns
150ns
CYCLE
CLK
MPA
MPD
MPCE
MPWE
MPOE
MPIRQ
Cycle 0
Cycle 1
Cycle 2
Cycle 3
Cycle 4
CONTROLREG(15:0) ADDRESS
0800h
tSA
tSCE
tH
tSWE
tH
tSD
tH
tSOE
tDIRQ
DS080_44_030501
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