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參數(shù)資料
| 型號： | XC866L-4RR |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash |
| 中文描述： | 8位微控制器與2/4/8K字節(jié)在系統(tǒng)可編程閃存 |
| 文件頁數(shù)： | 53/108頁 |
| 文件大?。?/td> | 979K |
| 代理商： | XC866L-4RR |
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XC866
Functional Description
Data Sheet
49
V1.0, 2006-02
3.7
Reset Control
The XC866 has five types of reset: power-on reset, hardware reset, watchdog timer
reset, power-down wake-up reset, and brownout reset.
When the XC866 is first powered up, the status of certain pins (see
Table 17
) must be
defined to ensure proper start operation of the device. At the end of a reset sequence,
the sampled values are latched to select the desired boot option, which cannot be
modified until the next power-on reset or hardware reset. This guarantees stable
conditions during the normal operation of the device.
In order to power up the system properly, the external reset pin RESET must be asserted
until
V
DDC
reaches 0.9*
V
DDC
. The delay of external reset can be realized by an external
capacitor at RESET pin. This capacitor value must be selected so that
V
RESET
reaches
0.4 V, but not before
V
DDC
reaches 0.9*
V
DDC.
A typical application example is shown in
Figure 20
. For a voltage regulator with IDD
max
= 100 mA, the
V
DDP
capacitor value is 10
μ
F. V
DDC
capacitor value is 220 nF. The
capacitor connected to RESET pin is 100 nF.
Typically, the time taken for
V
DDC
to reach 0.9*
V
DDC
is less than 50
μ
s once
V
DDP
reaches 2.3V. Hence, based on the condition that 10% to 90%
V
DDP
(slew rate) is less
than 500
μ
s, the RESET pin should be held low for 500
μ
s typically. See
Figure 21
.
Figure 20
Reset Circuitry
VSSP
VDDP
VDDC
VSSC
3.3V/5V
/
e.g. 100mA
RESET
EVR
VR
Vin
e.g. 10uF
220nF
typ.
100nF
XC866
30k
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