- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄4051 > XC4052XL-3HQ304I (Xilinx Inc)IC FPGA I-TEMP 3.3V 3SPD 304HQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | XC4052XL-3HQ304I |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 60/68頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA I-TEMP 3.3V 3SPD 304HQFP |
| 產(chǎn)品變化通告： | XC4000(XL,XLA,E) Discontinuation 15/Nov/2004 |
| 標(biāo)準(zhǔn)包裝： | 12 |
| 系列： | XC4000E/X |
| LAB/CLB數(shù)： | 1936 |
| 邏輯元件/單元數(shù)： | 4598 |
| RAM 位總計(jì)： | 61952 |
| 輸入/輸出數(shù)： | 256 |
| 門(mén)數(shù)： | 52000 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 304-BFQFP 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 304-PQFP（40x40） |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)當(dāng)前第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)
R
May 14, 1999 (Version 1.6)
6-67
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Figure 59: Asynchronous Peripheral Mode Programming Switching Characteristics
Previous Byte D6
D7
D0
D1
D2
1
TCA
2
TDC
4
TWTRB
3
TCD
6
TBUSY
READY
BUSY
RS, CS0
WS, CS1
D7
WS/CS0
RS, CS1
D0-D7
CCLK
RDY/BUSY
DOUT
Write to LCA
Read Status
X6097
7
4
Description
Symbol
Min
Max
Units
Write
Effective Write time
(CS0, WS=Low; RS, CS1=High)
1TCA
100
ns
DIN setup time
2
TDC
60
ns
DIN hold time
3
TCD
0ns
RDY
RDY/BUSY delay after end of
Write or Read
4TWTRB
60
ns
RDY/BUSY active after beginning
of Read
760
ns
RDY/BUSY Low output (Note 4)
6
TBUSY
2
9
CCLK
periods
Notes:
1. Conguration must be delayed until the INIT pins of all daisy-chained FPGAs are High.
2. The time from the end of WS to CCLK cycle for the new byte of data depends on the completion of previous byte
processing and the phase of the internal timing generator for CCLK.
3. CCLK and DOUT timing is tested in slave mode.
4. TBUSY indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest
TBUSY occurs when a byte is loaded into an empty parallel-to-serial converter. The longest TBUSY occurs when a new word
is loaded into the input register before the second-level buffer has started shifting out data
This timing diagram shows very relaxed requirements. Data need not be held beyond the rising edge of WS.RDY/BUSY will
go active within 60 ns after the end of WS. A new write may be asserted immediately after RDY/BUSY goes Low, but write
may not be terminated until RDY/BUSY has been High for one CCLK period.
Product Obsolete or Under Obsolescence
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 65801-031LF | CLINCHER RECEPTACLE ASSY TIN |
| FMC31DREF-S13 | CONN EDGECARD 62POS .100 EXTEND |
| FMC25DREI-S93 | CONN EDGECARD 50POS .100 EYELET |
| MC7448VU867ND | IC MPU RISC 32BIT 360-FCCBGA |
| MPC8535AVTATHA | MPU POWERQUICC III 783FCPBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC4052XLA-07HQ208C | 制造商:Xilinx 功能描述: |
| XC4052XLA-08BG432C | 制造商:Rochester Electronics LLC 功能描述: 制造商:Xilinx 功能描述: |
| XC4052XLA-08HQ160I | 制造商:Xilinx 功能描述: |
| XC4052XLA-08HQ240C | 制造商:Xilinx 功能描述: |
| XC4052XLA-09BG352I | 制造商:Xilinx from Components Direct 功能描述:XC4052XLA-09BG352I, FPGA XC4000XLA - Trays 制造商:Xilinx 功能描述:Xilinx XC4052XLA-09BG352I, FPGA XC4000XLA Family 52K Gates 4598 Cells 227MHz 0.35um (CMOS) Technology 3.3V 352-Pin BGA |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。