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參數(shù)資料
| 型號： | XC3SD1800A-4CSG484LI |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 41/101頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA SPARTAN 3 DSP 484CSGBGA |
| 標準包裝： | 84 |
| 系列： | Spartan®-3A DSP |
| LAB/CLB數(shù)： | 4160 |
| 邏輯元件/單元數(shù)： | 37440 |
| RAM 位總計： | 1548288 |
| 輸入/輸出數(shù)： | 309 |
| 門數(shù)： | 1800000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 484-FBGA，CSPBGA |
| 供應商設備封裝： | 484-CSPBGA |
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Spartan-3A DSP FPGA Family: DC and Switching Characteristics
DS610 (v3.0) October 4, 2010
Product Specification
44
Digital Clock Manager (DCM) Timing
For specification purposes, the DCM consists of three key
components: the Delay-Locked Loop (DLL), the Digital
Frequency Synthesizer (DFS), and the Phase Shifter (PS).
Aspects of DLL operation play a role in all DCM
applications. All such applications inevitably use the CLKIN
and the CLKFB inputs connected to either the CLK0 or the
CLK2X feedback, respectively. Thus, specifications in the
that only employs the DLL component. When the DFS
and/or the PS components are used together with the DLL,
then the specifications listed in the DFS and PS tables
ones in the DLL tables. DLL specifications that do not
change with the addition of DFS or PS functions are
Period jitter and cycle-cycle jitter are two of many different
ways of specifying clock jitter. Both specifications describe
statistical variation from a mean value.
Period jitter is the worst-case deviation from the ideal clock
period over a collection of millions of samples. In a
histogram of period jitter, the mean value is the clock period.
Cycle-cycle jitter is the worst-case difference in clock period
between adjacent clock cycles in the collection of clock
periods sampled. In a histogram of cycle-cycle jitter, the
mean value is zero.
Spread Spectrum
DCMs accept typical spread spectrum clocks as long as
they meet the input requirements. The DLL will track the
frequency changes created by the spread spectrum clock to
drive the global clocks to the FPGA logic. See XAPP469:
Spread-Spectrum Clocking Reception for Displays for
details.
Delay-Locked Loop (DLL)
Table 36: Recommended Operating Conditions for the DLL
Symbol
Description
Speed Grade
Units
-5
-4
Min
Max
Min
Max
Input Frequency Ranges
FCLKIN
CLKIN_FREQ_DLL
Frequency of the CLKIN clock input
280(3)
5(2)
250(3)
MHz
Input Pulse Requirements
CLKIN_PULSE
CLKIN pulse width as a
percentage of the CLKIN
period
FCLKIN < 150 MHz
40%
60%
40%
60%
–
FCLKIN > 150 MHz
45%
55%
45%
55%
–
Input Clock Jitter Tolerance and Delay Path Variation(4)
CLKIN_CYC_JITT_DLL_LF
Cycle-to-cycle jitter at the
CLKIN input
FCLKIN < 150 MHz
–±300
ps
CLKIN_CYC_JITT_DLL_HF
FCLKIN > 150 MHz
–±150
ps
CLKIN_PER_JITT_DLL
Period jitter at the CLKIN input
–±1
ns
CLKFB_DELAY_VAR_EXT
Allowable variation of off-chip feedback delay
from the DCM output to the CLKFB input
–±1
ns
Notes:
1.
DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.
2.
The DFS, when operating independently of the DLL, supports lower FCLKIN frequencies. See Table 38.
3.
To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming
clock frequency by two as it enters the DCM. The CLK2X output reproduces the clock frequency provided on the CLKIN input.
4.
CLKIN input jitter beyond these limits might cause the DCM to lose lock.
5.
The DCM specifications are guaranteed when both adjacent DCMs are locked.
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