參數(shù)資料
型號： XC3SD1800A-4CSG484LI
廠商： Xilinx Inc
文件頁數(shù)： 16/101頁
文件大?。?/td> 0K
描述： IC FPGA SPARTAN 3 DSP 484CSGBGA
標準包裝： 84
系列： Spartan®-3A DSP
LAB/CLB數(shù)： 4160
邏輯元件/單元數(shù)： 37440
RAM 位總計： 1548288
輸入/輸出數(shù)： 309
門數(shù)： 1800000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 484-FBGA，CSPBGA
供應商設(shè)備封裝： 484-CSPBGA
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
DS610 (v3.0) October 4, 2010
Product Specification
21
Pin-to-Pin Setup and Hold Times
Table 18: Pin-to-Pin Setup and Hold Times for the IOB Input Path (System Synchronous)
Symbol
Description
Conditions
Device
Speed Grade
Units
-5
-4
Max
Setup Times
TPSDCM
When writing to the Input
Flip-Flop (IFF), the time from
the setup of data at the Input pin
to the active transition at a
Global Clock pin. The DCM is in
use. No Input Delay is
programmed.
LVCMOS25(2),
IFD_DELAY_VALUE = 0,
with DCM(4)
XC3SD1800A
2.65
3.11
ns
XC3SD3400A
2.25
2.49
ns
TPSFD
When writing to IFF, the time
from the setup of data at the
Input pin to an active transition
at the Global Clock pin. The
DCM is not in use. The Input
Delay is programmed.
LVCMOS25(2),
IFD_DELAY_VALUE = 6,
without DCM
XC3SD1800A
2.98
3.39
ns
XC3SD3400A
2.78
3.08
ns
Hold Times
TPHDCM
When writing to IFF, the time
from the active transition at the
Global Clock pin to the point
when data must be held at the
Input pin. The DCM is in use.
No Input Delay is programmed.
LVCMOS25(3),
IFD_DELAY_VALUE = 0,
with DCM(4)
XC3SD1800A
–0.38
ns
XC3SD3400A
–0.26
ns
TPHFD
When writing to IFF, the time
from the active transition at the
Global Clock pin to the point
when data must be held at the
Input pin. The DCM is not in
use. The Input Delay is
programmed.
LVCMOS25(3),
IFD_DELAY_VALUE = 6,
without DCM
XC3SD1800A
–0.71
ns
XC3SD3400A
–0.65
ns
Notes:
1.
The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in
2.
This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from Table 22. If this is true of the data Input, add the
appropriate Input adjustment from the same table.
3.
This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from Table 22. If this is true of the data Input, subtract the
appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
4.
DCM output jitter is included in all measurements.
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