參數(shù)資料
型號: WED9LC6816V1610BI
廠商: WHITE ELECTRONIC DESIGNS CORP
元件分類: 存儲器
英文描述: SPECIALTY MEMORY CIRCUIT, PBGA153
封裝: 14 X 22 MM, MO-163, BGA-153
文件頁數(shù): 9/26頁
文件大?。?/td> 324K
代理商: WED9LC6816V1610BI
WED9LC6816V
17
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
September, 2003
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specications without notice.
FIG. 9 SDRAM PAGE READ CYCLE AT DIFFERENT BANK @
BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCK
SDWE#
SDCAS#
ADDR
RAa
RBb
CAa
CBb
CAe
CBd
CAc
BA0, 1
[A12,A13]
SDA10
RAa
RBb
CL=2
QAa1
QAa0
QAa2 QAa3 QBb0 QBb1 QBb2
QAc1
QBb3 QAc0
QBd0 QBd1 QAe0 QAe1
CL=3
DQ
QAa1
QAa0
QAa2 QAa3 QBb0 QBb1
QAc0
QBb2
Qbb3
QAc1 QBd0 QBd1
QAe0 QAe1
Row Active
(A-Bank)
Row Active
(B-Bank)
Read
(A-Bank)
Read
(B-Bank)
Read
(A-Bank)
Read
(B-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
DON’T CARE
SDCE#
SDRAS#
BWE#
Note 2
Note 1
NOTES:
1. SDCE# can be “don’t care” when SDRAS#, SDCAS# and SDWE# are high at the clock going high edge.
2. To interrupt a burst read by Row precharge, both the read and the precharge banks must be the same.
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