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參數(shù)資料
| 型號： | W987X6CBG80 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54 |
| 封裝： | 8 X 9 MM, 1.20 MM HEIGHT, FBGA-54 |
| 文件頁數(shù)： | 42/46頁 |
| 文件大?。?/td> | 1634K |
| 代理商： | W987X6CBG80 |
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Preliminary W987X6CB
Publication Release Date: June 6, 2002
- 5 -
Revision A1
5. BALL DESCRIPTION
PIN NUMBER
BALL NAME
FUNCTION
DESCRIPTION
H7, H8, J8, J7,
J3, J2, H3, H2,
H1, G3, H9, G2
A0
A11
Address
Multiplexed pins for row and column address.
Row address: A0
A11. Column address: A0 A8.
G7, G8
BS0, BS1
Bank Select
Select bank to activate during row address latch
time, or bank to read/write during address latch
time.
A8, B9, B8, C9,
C8, D9, D8, E9,
E1, D2 D1, C2,
C1, B2, B1, A2
DQ0
DQ15
Data Input/
Output
Multiplexed pins for data output and input.
G9
CS
Chip Select
Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
F8
RAS
Row Address
Strobe
Command input. When sampled at the rising edge
of the clock, RAS , CAS and WE define the
operation to be executed.
F7
CAS
Column
Address Strobe
Referred to RAS
F9
WE
Write Enable
Referred to RAS
F1, E8
UDQM
LDQM
Input/Output
Mask
The output buffer is placed at Hi-Z (with latency of
2) when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.
F2
CLK
Clock Inputs
System clock used to sample inputs on the rising
edge of clock.
F3
CKE
Clock Enable
CKE controls the clock activation and deactivation.
When CKE is low, Power Down mode, Suspend
mode or Self Refresh mode is entered.
A9, E7, J9
VDD
Power
Power for input buffers and logic circuit inside
DRAM.
A1, E3, J1
VSS
Ground
Ground for input buffers and logic circuit inside
DRAM.
A7, B3, C7, D3
VDDQ
Power for I/O
Buffer
Separated power from VCC, used for output buffers
to improve noise.
A3, B7, C3, D7
VSSQ
Ground for I/O
Buffer
Separated ground from VSS, used for output buffers
to improve noise.
E2, G1
NC
No Connection No connection
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