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參數(shù)資料
| 型號(hào)： | W987X6CBG80 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54 |
| 封裝： | 8 X 9 MM, 1.20 MM HEIGHT, FBGA-54 |
| 文件頁(yè)數(shù)： | 3/46頁(yè) |
| 文件大?。?/td> | 1634K |
| 代理商： | W987X6CBG80 |
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Preliminary W987X6CB
Publication Release Date: June 6, 2002
- 11 -
Revision A1
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 1 shows the truth table for the operation commands.
Table 1 Truth Table (Note (1), (2))
COMMAND
DEVICE
STATE
CKEn-1
CKEn
DQM
BS0, 1
A10
A0
A9
A11
CS
RAS
CAS
WE
Bank Active
Idle
H
x
v
L
H
Bank Precharge
Any
H
x
v
L
x
L
H
L
Precharge All
Any
H
x
H
x
L
H
L
Write
Active (3)
H
x
v
L
v
L
H
L
Write with
Autoprecharge
Active (3)
H
x
v
H
v
L
H
L
Read
Active (3)
H
x
v
L
v
L
H
L
H
Read with
Autoprecharge
Active (3)
H
x
v
H
v
L
H
L
H
Mode Register Set
Idle
H
x
v
L
No – Operation
Any
H
x
L
H
Burst Stop
Active (4)
H
x
L
H
L
Device Deselect
Any
H
x
H
x
Auto – Refresh
Idle
H
x
L
H
Self - Refresh Entry
Idle
H
L
x
L
H
Self Refresh Exit
idle
(S.R.)
L
H
x
H
L
x
H
x
H
x
Clock suspend Entry
Active
H
L
x
Power Down Entry
Idle
Active (5)
H
L
x
H
L
x
H
x
H
x
Clock Suspend Exit
Active
L
H
x
Power Down Exit
Any
(power down)
L
H
x
H
L
x
H
x
H
x
Deep Power Down
Entry
Idle
H
L
x
L
H
L
Deep Power Down Exit
DPDM
L
H
x
Data write/Output
Enable
Active
H
x
L
x
Data write/Output
Disable
Active
H
x
H
x
Notes:
1.
V = Valid
X = Don't care
L = Low Level
H = High Level
2.
CKEn signal is input level when commands are provided. CKEn-1 signal is the input level one clock cycle before the
command is issued.
3.
These are state of bank designated by BS0, BS1 signals.
4.
Device state is full page burst operation.
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