參數(shù)資料
型號： W986432EH-7
廠商： WINBOND ELECTRONICS CORP
元件分類： DRAM
英文描述： 2M X 32 SYNCHRONOUS DRAM, 5.5 ns, PDSO86
封裝： 0.400 INCH, TSOP2-86
文件頁數(shù)： 12/48頁
文件大?。?/td> 1180K
代理商： W986432EH-7
W986432EH / W9864G2EH
- 2 -
13.
AC CHARACTERISTICS .......................................................................................................... 16
14.
TIMING WAVEFORMS ............................................................................................................. 19
14.1
Command Input Timing ................................................................................................ 19
14.2
Read Timing.................................................................................................................. 20
14.3
Control Timing of Input Data......................................................................................... 21
14.4
Control Timing of Output Data ...................................................................................... 22
14.5
Mode Register Set Cycle .............................................................................................. 23
15.
OPERATING TIMING EXAMPLE ............................................................................................. 24
15.1
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)...................................... 24
15.2
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Autoprecharge) ............ 25
15.3
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)...................................... 26
15.4
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Autoprecharge) ............ 27
15.5
Interleaved Bank Write (Burst Length = 8) ................................................................... 28
15.6
Interleaved Bank Write (Burst Length = 8, Autoprecharge).......................................... 29
15.7
Page Mode Read (Burst Length = 4, CAS Latency = 3)............................................... 30
15.8
Page Mode Read/Write (Burst Length = 8, CAS Latency = 3) ..................................... 31
15.9
Autoprecharge Read (Burst Length = 4, CAS Latency = 3) ......................................... 32
15.10 Autoprecharge Write (Burst Length = 4)....................................................................... 33
15.11 Autorefresh Cycle ......................................................................................................... 34
15.12 Self-refresh Cycle ......................................................................................................... 35
15.13 Bust Read and Single Write (Burst Length = 4, CAS Latency = 3) .............................. 36
15.14 Power-down Mode........................................................................................................ 37
15.15 Auto-precharge Timing (Write Cycle) ........................................................................... 38
15.16 Auto-precharge Timing (Read Cycle) ........................................................................... 39
15.17 Timing Chart of Read to Write Cycle ............................................................................ 40
15.18 Timing Chart of Write to Read Cycle ............................................................................ 41
15.19 Timing Chart of Burst Stop Cycle (Burst Stop Command) ........................................... 42
15.20 Timing Chart of Burst Stop Cycle (Precharge Command) ........................................... 43
15.21 CKE/DQM Input Timing (Write Cycle) .......................................................................... 44
15.22 CKE/DQM Input Timing (Read Cycle) .......................................................................... 45
15.23 Self Refresh/Power Down Mode Exit Timing................................................................ 46
16.
PACKAGE DIMENSIONS......................................................................................................... 47
16.1
86L TSOP (II)-400 mil................................................................................................... 47
17.
REVISION HISTORY ................................................................................................................48
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