參數(shù)資料
型號： W29GL064CB7S
廠商： WINBOND ELECTRONICS CORP
元件分類： PROM
英文描述： 64M X 1 FLASH 3V PROM, 70 ns, PDSO48
封裝： 12 X 20 MM, GREEN, TSOP-48
文件頁數(shù)： 13/65頁
文件大?。?/td> 648K
代理商： W29GL064CB7S
W29GL064C
14
7.2.20
Enhanced Variable IO (
EVIO) Control
The Enhanced Variable IO (EVIO) control allows the host system to set the voltage levels that the
device generates and tolerates on all inputs and outputs (address, control, and DQ signals). EVIO
range is 1.65 to VCC.
For example, a EVIO of 1.65-3.6 volts allows for I/O at the 1.8 or 3 volt levels, driving and receiving
signals to and from other 1.8 or 3 V devices on the same data bus.
7.2.21 Hardware Data Protection Options
Hardware Data Protection is the second of the two main sector protections offered by the W29GL064.
7.2.21.1
#WP/ACC Option
By setting the #WP/ACC pin to VIL, the highest or lowest sector (device specific) is protected from all
erase/program operations. If #WP/ACC is set High, the highest and Lowest sector revert back to the
previous protected/unprotected state.
Note: The max input load current can increase, if #WP/ACC pin is at VIH when the device is put into
standby mode.
7.2.21.2
VCC Write Protect
This device will not accept any write instructions when VCC is less that VWPT (VCC Write Protect
Threshold)). This prevents data from inadvertently being altered during power-up, power-down, a
temporary power loss or to the low level of VCC. If VCC is lower that VWPT, the device automatically
resets itself and will ignore write cycles until VCC is greater than VWPT. Once VCC rises above VWPT,
insure that the proper signals are on the control pins to avoid unexpected program or erase operations.
7.2.21.3
Write Pulse “Glitch” Protection
Pulses less than 5ns are viewed as glitches for control signals #CE, #WE, and #OE and will not be
considered for valid write cycles.
7.2.21.4
Power-up Write Inhibit
The device ignores the first instruction on the rising edge of #WE, if upon powering up the device,
#WE and #CE are set at VIL and #OE is set at VIH.
7.2.21.5
Logical Inhibit
A write cycle is ignored when either #CE is at VIH, #WE is at VIH, or #OE is at VIL. A valid write cycle
requires both #CE and #WE are at VIL with #OE at VIH.
7.2.22 Inherent Data Protection
The device built-in mechanism will reset to Read mode during power up to avoid accidental erasure or
programming.
7.2.22.1
Instruction Completion
Invalid instruction sets will result in the memory returning to read mode. Only upon a successful
completion of a valid instruction set will the device begin its erase or program operation..
7.2.22.2
Power-up Sequence
The device is placed in Read mode, during power-up sequence.
7.2.23 Power Supply Decoupling
To reduce noise effects, a 0.1F capacitor is recommended to be connected between VCC and GND.
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參數(shù)描述
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