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參數(shù)資料
| 型號： | W28F321TB70L |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 2M X 16 FLASH 1.8V PROM, 70 ns, PBGA48 |
| 封裝： | 7 X 7 MM, 0.75 MM PITCH, TFBGA-48 |
| 文件頁數(shù)： | 4/28頁 |
| 文件大?。?/td> | 372K |
| 代理商： | W28F321TB70L |
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W28F321BB/TB
- 12 -
Table 10. Status Register Definition
R
15
14
13
12
11
10
9
8
WSMS
BESS
BEFCES
PBPOPS
VPPS
PBPSS
DPS
R
7
6
5
4
3
2
1
0
SR.15 - SR.8 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
SR.6 = BLOCK ERASE SUSPEND STATUS (BESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5 = BLOCK ERASE AND FULL CHIP ERASE STATUS
(BEFCES)
1 = Error in Block Erase or Full Chip Erase
0 = Successful Block Erase or Full Chip Erase
SR.4 = (PAGE BUFFER) PROGRAM AND OTP PROGRAM
STATUS (PBPOPS)
1 = Error in (Page Buffer) Program or OTP Program
0 = Successful (Page Buffer) Program or OTP Program
SR.3 = VPP STATUS (VPPS)
1 = VPP LOW Detect, Operation Abort
0 = VPP OK
SR.2 = (PAGE BUFFER) PROGRAM SUSPEND STATUS
(PBPSS)
1 = (Page Buffer) Program Suspended
0 = (Page Buffer) Program in Progress/Completed
SR.1 = DEVICE PROTECT STATUS (DPS)
1 = Erase or Program Attempted on a Locked Block,
Operation Abort
0 = Unlocked
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
NOTES:
Status Register indicates the status of the partition, not WSM
(Write State Machine). Even if the SR.7 is "1", the WSM may
be occupied by the other partition when the device is set to
2, 3 or 4 partitions configuration.
Check SR.7 to determine block erase, full chip erase, (page
buffer) program or OTP program completion. SR.6
SR.1
are invalid while SR.7 = "0".
If both SR.5 and SR.4 are "1"s after a block erase, full chip
erase, (page buffer) program, set/clear block lock bit, set
block lock-down bit, set partition configuration register
attempt, an improper command sequence was entered.
SR.3 does not provide a continuous indication of VPP level.
The WSM interrogates and indicates the VPP level only after
Block Erase, Full Chip Erase, (Page Buffer) Program or OTP
Program command sequences. SR.3 is not guaranteed to
report accurate feedback when VPP
≠ VPPH1, VPPH2 or VPPLK.
SR.1 does not provide a continuous indication of block lock
bit. The WSM interrogates the block lock bit only after Block
Erase, Full Chip Erase, (Page Buffer) Program or OTP
Program command sequences. It informs the system,
depending on the attempted operation, if the block lock bit is
set. Reading the block lock configuration codes after writing
the Read Identifier Codes/OTP command indicates block
lock bit status.
SR.15 - SR.8 and SR.0 are reserved for future use and
should be masked out when polling the status register.
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