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參數(shù)資料
| 型號： | W28F321TB70L |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 2M X 16 FLASH 1.8V PROM, 70 ns, PBGA48 |
| 封裝： | 7 X 7 MM, 0.75 MM PITCH, TFBGA-48 |
| 文件頁數(shù)： | 28/28頁 |
| 文件大小： | 372K |
| 代理商： | W28F321TB70L |
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W28F321BB/TB
Publication Release Date: February 17, 2003
- 9 -
Revision A2
Table 6. Command Definitions(11)
FIRST BUS CYCLE
SECOND BUS CYCLE
COMMAND
BUS
CYCLES
REQ’D.
NOTE
Oper(1) Addr(2) Data(3) Oper(1) Addr(2) Data(3)
Read Array
1
2
Write
PA
FFH
Read Identifier Codes/OTP
≥ 2
2, 3, 4
Write
PA
90H
Read
IA or OA ID or OD
Read Query
≥ 2
2, 3, 4
Write
PA
98H
Read
QA
QD
Read Status Register
2
2, 3
Write
PA
70H
Read
PA
SRD
Clear Status Register
1
2
Write
PA
50H
Block Erase
2
2, 3, 5
Write
BA
20H
Write
BA
D0H
Full Chip Erase
2
2, 5, 9
Write
X
30H
Write
X
D0H
Program
2
2, 3, 5, 6
Write
WA
40H or
10H
Write
WA
WD
Page Buffer Program
≥ 4
2, 3, 5, 7
Write
WA
E8H
Write
WA
N-1
Block Erase and (Page Buffer)
Program Suspend
1
2, 8, 9
Write
PA
B0H
Block Erase and (Page Buffer)
Program Resume
1
2, 8, 9
Write
PA
D0H
Set Block Lock Bit
2
Write
BA
60H
Write
BA
01H
Clear Block Lock Bit
2
2, 10
Write
BA
60H
Write
BA
D0H
Set Block Lock-down Bit
2
Write
BA
60H
Write
BA
2FH
OTP Program
2
2, 3, 9
Write
OA
C0H
Write
OA
OD
Set Partition configuration
Register
2
2, 3
Write
PCRC
60H
Write
PCRC
04H
Notes:
1. Bus operations are defined in Table 5.
2. The address which is written at the first bus cycle should be the same as the address which is written at the second bus cycle.
X = Any valid address within the device.
PA = Address within the selected partition.
IA = Identifier codes address (See Table 3 and Table 4).
QA = Query codes address. Refer to Appendix for details.
BA = Address within the block being erased, set/cleared block lock bit or set block lock-down bit.
WA = Address of memory location for the Program command or the first address for the Page Buffer Program command.
OA = Address of OTP block to be read or programmed (See Figure 3).
PCRC = Partition configuration register code presented on the address A0
A15.
3. ID = Data read from identifier codes. (See Table 3 and Table 4).
QD = Data read from query database. Refer to Appendix for details.
SRD = Data read from status register. See Table 10 and Table 11 for a description of the status register bits.
WD = Data to be programmed at location WA. Data is latched on the rising edge of #WE or #CE (whichever goes high first).
OD = Data to be programmed at location OA. Data is latched on the rising edge of #WE or #CE (whichever goes high first).
N-1 = N is the number of the words to be loaded into a page buffer.
4. Following the Read Identifier Codes/OTP command, read operations access manufacturer code, device code, block lock
configuration code, partition configuration register code and the data within OTP block (See Table 3 and Table 4). The Read
Query command is available for reading CFI (Common Flash Interface) information.
5. Block erase, full chip erase or (page buffer) program cannot be executed when the selected block is locked. Unlocked block
can be erased or programmed when #RESET is VIH.
6. Either 40H or 10H are recognized by the CUI (Command User Interface) as the program setup.
7. Following the third bus cycle, inputs the program sequential address and write data of "N" times. Finally, input the any valid
address within the target partition to be programmed and the confirm command (D0H). Refer to Appendix for details.
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