參數(shù)資料
型號(hào)： W28F321TB70L
廠商： WINBOND ELECTRONICS CORP
元件分類(lèi)： PROM
英文描述： 2M X 16 FLASH 1.8V PROM, 70 ns, PBGA48
封裝： 7 X 7 MM, 0.75 MM PITCH, TFBGA-48
文件頁(yè)數(shù)： 10/28頁(yè)
文件大?。?/td> 372K
代理商： W28F321TB70L
W28F321BB/TB
- 18 -
DC Characteristics (continued)
VDD = 2.7V 3.6V
PARAMETER
SYM.
TEST
CONDITIONS
Min.
Typ.
Max.
UNIT
Input Low Voltage (note 5)
VIL
-0.4
0.4
V
Input High Voltage (note 5)
VIH
VDDQ
-0.4
VDDQ
+0.4
V
Output Low Voltage (note 5)
VOL
VDD = VDD Min., VDDQ =
VDDQ Min., IOL = 100 A
0.2
V
Output High Voltage (note 5)
VOH
VDD = VDD Min., VDDQ =
VDDQ Min., IOH = -100 A
VDDQ
-0.2
V
VPP Lockout during Normal Operations
(note 3, 5, 6)
VPPLK
0.4
V
VPP during Block Erase, Full Chip Erase,
(Page Buffer) Program or OTP Program
Operations (note 6)
VPPH1
1.65
3.0
3.6
V
VPP during Block Erase, (Page Buffer)
Program or OTP Program Operations
(note 6)
VPPH2
11.7
12
12.3
V
VDD Lockout Voltage
VLKO
1.5
V
Notes:
1. All currents are in RMS unless otherwise noted. Typical values are the reference values at VDD = 3.0V and TA = +25° C unless
VDD is specified.
2. ICCWS and ICCES are specified with the device de-selected. If read or (page buffer) program while in block erase suspend
mode, the device's current draw is the sum of ICCWS or ICCES and ICCR or ICCW, respectively.
3. Block erases, full chip erase, (page buffer) program and OTP program are inhibited when VPP ≤ VPPLK, and not guaranteed in
the range between VPPLK (max.) and VPPH1 (min.), between VPPH1 (max.) and VPPH2 (min.) and above VPPH2 (max.).
4. The Automatic Power Savings (APS) feature automatically places the device in power save mode after read cycle completion.
Standard address access timings (tAVQV) provide new data when address are changed.
5. Sampled, not 100% tested.
6. VPP is not used for power supply pin. With VPP ≤ VPPLK, block erase, full chip erase, (page buffer) program and OTP program
cannot be executed and should not be attempted.
Applying 12V±0.3V to V VPP provides fast erasing or fast programming mode. In this mode, VPP is power supply pin and
supplies the memory cell current for block erasing and (page buffer) programming. Use similar power supply trace widths and
layout considerations given to the VDD power bus.
Applying 12V±0.3V to VPP during erase/program can only be done for a maximum of 1,000 cycles on each block. VPP may be
connected to 12V±0.3V for a total of 80 hours maximum.
7. The operating current in dual work is the sum of the operating current (read, erase, program) in each plane.
相關(guān)PDF資料
PDF描述
W29C010-70 128K X 8 FLASH 5V PROM, 70 ns, PDIP32
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